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The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort Subsystem. It includes a buffer manager, blender, an audio mixer and a DisplayPort source controller (transmitter). The DisplayPort controller can source data from memory (non-live input) or the stream (live input). The DisplayPort controller is responsible for managing the link and physical layer functionality. The controller packs audio/video data into transfer units and sends them over the main link. The link rate and lane counts can be selected based on the application bandwidth requirements. The DisplayPort pipeline consists of the DisplayPort direct memory access (DMA) for fetching data from memory. The DisplayPort DMA controller (DPDMA) supports up to six input channels as non-live input. This driver supports the DisplayPort Subsystem and implements 1)640x480 resolution 2)RGBA8888 32bpp format 3)DPDMA channel 3 for Graphics 4)Non-live input 5)Fixed 5.4G link rate 6)Tested on ZCU102 board There will be additional work to configure GT lines based on DT, higher resolutions, support for more compressed video formats, spliting code to more files, add support for EDID, audio support, using clock framework for all clocks and in general code clean up. Codevelop-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5c1567b63d0280dacc7efba2998857c399c25358.1684312924.git.michal.simek@amd.com |
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| Kconfig | ||
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| zynqmp_dpsub.c | ||
| zynqmp_dpsub.h | ||