mirror of
https://github.com/AsahiLinux/u-boot
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307 lines
6.7 KiB
C
307 lines
6.7 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2002,2003, Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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void local_bus_init(void);
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void sdram_init(void);
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long int fixed_sdram(void);
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int checkboard (void)
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{
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puts("Board: ADS\n");
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#ifdef CONFIG_PCI
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printf(" PCI1: 32 bit, %d MHz (compiled)\n",
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CONFIG_SYS_CLK_FREQ / 1000000);
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#else
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printf(" PCI1: disabled\n");
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#endif
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/*
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* Initialize local bus.
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*/
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local_bus_init();
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return 0;
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}
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phys_size_t
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initdram(int board_type)
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{
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long dram_size = 0;
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puts("Initializing\n");
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#if defined(CONFIG_DDR_DLL)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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uint temp_ddrdll = 0;
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/*
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* Work around to stabilize DDR DLL
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*/
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temp_ddrdll = gur->ddrdllcr;
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gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
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asm("sync;isync;msync");
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}
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#endif
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#ifdef CONFIG_SPD_EEPROM
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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#else
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dram_size = fixed_sdram();
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(dram_size);
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#endif
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/*
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* Initialize SDRAM.
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*/
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sdram_init();
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puts(" DDR: ");
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return dram_size;
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}
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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uint clkdiv;
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uint lbc_hz;
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sys_info_t sysinfo;
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/*
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* Errata LBC11.
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* Fix Local Bus clock glitch when DLL is enabled.
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*
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* If localbus freq is < 66Mhz, DLL bypass mode must be used.
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* If localbus freq is > 133Mhz, DLL can be safely enabled.
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* Between 66 and 133, the DLL is enabled with an override workaround.
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*/
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get_sys_info(&sysinfo);
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clkdiv = lbc->lcrr & 0x0f;
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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if (lbc_hz < 66) {
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lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */
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} else if (lbc_hz >= 133) {
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lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
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} else {
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/*
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* On REV1 boards, need to change CLKDIV before enable DLL.
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* Default CLKDIV is 8, change it to 4 temporarily.
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*/
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uint pvr = get_pvr();
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uint temp_lbcdll = 0;
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if (pvr == PVR_85xx_REV1) {
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/* FIXME: Justify the high bit here. */
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lbc->lcrr = 0x10000004;
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}
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lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
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udelay(200);
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/*
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* Sample LBC DLL ctrl reg, upshift it to set the
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* override bits.
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*/
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temp_lbcdll = gur->lbcdllcr;
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gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
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asm("sync;isync;msync");
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}
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}
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void
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sdram_init(void)
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{
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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puts(" SDRAM: ");
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print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
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/*
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* Setup SDRAM Base and Option Registers
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*/
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lbc->or2 = CONFIG_SYS_OR2_PRELIM;
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lbc->br2 = CONFIG_SYS_BR2_PRELIM;
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lbc->lbcr = CONFIG_SYS_LBC_LBCR;
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asm("msync");
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lbc->lsrt = CONFIG_SYS_LBC_LSRT;
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lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
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asm("sync");
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/*
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* Configure the SDRAM controller.
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*/
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
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asm("sync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
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asm("sync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
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asm("sync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
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asm("sync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
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asm("sync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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long int fixed_sdram (void)
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{
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#ifndef CONFIG_SYS_RAMBOOT
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volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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#if defined (CONFIG_DDR_ECC)
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ddr->err_disable = 0x0000000D;
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ddr->err_sbe = 0x00ff0000;
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#endif
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asm("sync;isync;msync");
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udelay(500);
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#if defined (CONFIG_DDR_ECC)
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/* Enable ECC checking */
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ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
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#else
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
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#endif
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asm("sync; isync; msync");
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udelay(500);
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#endif
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI Devices, report devices found.
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*/
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static struct pci_controller hose;
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#endif /* CONFIG_PCI */
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void
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pci_init_board(void)
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{
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#ifdef CONFIG_PCI
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pci_mpc85xx_init(&hose);
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#endif /* CONFIG_PCI */
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void
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ft_board_setup(void *blob, bd_t *bd)
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{
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int node, tmp[2];
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const char *path;
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ft_cpu_setup(blob, bd);
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node = fdt_path_offset(blob, "/aliases");
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tmp[0] = 0;
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if (node >= 0) {
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#ifdef CONFIG_PCI
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path = fdt_getprop(blob, node, "pci0", NULL);
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if (path) {
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tmp[1] = hose.last_busno - hose.first_busno;
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do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
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}
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#endif
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}
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}
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#endif
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