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SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
77 lines
1.6 KiB
C
77 lines
1.6 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#include <common.h>
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#include <malloc.h>
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#include "jobdesc.h"
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#include "desc.h"
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#include "jr.h"
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#define CRYPTO_MAX_ALG_NAME 80
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#define SHA1_DIGEST_SIZE 20
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#define SHA256_DIGEST_SIZE 32
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struct caam_hash_template {
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char name[CRYPTO_MAX_ALG_NAME];
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unsigned int digestsize;
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u32 alg_type;
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};
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enum caam_hash_algos {
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SHA1 = 0,
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SHA256
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};
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static struct caam_hash_template driver_hash[] = {
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{
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.name = "sha1",
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.digestsize = SHA1_DIGEST_SIZE,
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.alg_type = OP_ALG_ALGSEL_SHA1,
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},
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{
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.name = "sha256",
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.digestsize = SHA256_DIGEST_SIZE,
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.alg_type = OP_ALG_ALGSEL_SHA256,
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},
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};
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int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
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unsigned char *pout, enum caam_hash_algos algo)
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{
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int ret = 0;
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uint32_t *desc;
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desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
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if (!desc) {
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debug("Not enough memory for descriptor allocation\n");
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return -1;
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}
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inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout,
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driver_hash[algo].alg_type,
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driver_hash[algo].digestsize,
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0);
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ret = run_descriptor_jr(desc);
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free(desc);
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return ret;
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}
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void hw_sha256(const unsigned char *pbuf, unsigned int buf_len,
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unsigned char *pout, unsigned int chunk_size)
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{
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if (caam_hash(pbuf, buf_len, pout, SHA256))
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printf("CAAM was not setup properly or it is faulty\n");
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}
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void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
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unsigned char *pout, unsigned int chunk_size)
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{
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if (caam_hash(pbuf, buf_len, pout, SHA1))
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printf("CAAM was not setup properly or it is faulty\n");
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}
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