u-boot/arch/riscv
Sagar Shrikant Kadam d04a46426b sifive: reset: add DM based reset driver for SiFive SoC's
PRCI module within SiFive SoC's has register with which we can
reset the sub-systems within the SoC. The resets to DDR and ethernet
sub systems within FU540-C000 SoC are active low, and are hold low
by default on power-up. Currently these are directly asserted within
prci driver via register read/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2020-08-04 09:19:41 +08:00
..
cpu riscv: Fix linking error when building u-boot-spl with no SMP support 2020-07-24 14:56:13 +08:00
dts fu540: dtsi: add reset producer and consumer entries 2020-08-04 09:19:41 +08:00
include/asm sifive: reset: add DM based reset driver for SiFive SoC's 2020-08-04 09:19:41 +08:00
lib Revert "riscv: Allow use of reset drivers" 2020-07-24 14:55:31 +08:00
config.mk kconfig / kbuild: Re-sync with Linux 4.19 2020-04-10 11:18:32 -04:00
Kconfig Merge branch 'next' 2020-07-06 15:46:38 -04:00
Makefile riscv: add Kconfig entries for the code model 2018-12-18 09:56:26 +08:00