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643cf0ea02
This patch adds the basic clocks and timer support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Some of the code here is common to multiple sunxi subarchtectures, hence files are named sun4i which is the earliest similar variant. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
256 lines
8.3 KiB
C
256 lines
8.3 KiB
C
/*
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* sun4i, sun5i and sun7i clock register definitions
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_CLOCK_SUN4I_H
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#define _SUNXI_CLOCK_SUN4I_H
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struct sunxi_ccm_reg {
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u32 pll1_cfg; /* 0x00 pll1 control */
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u32 pll1_tun; /* 0x04 pll1 tuning */
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u32 pll2_cfg; /* 0x08 pll2 control */
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u32 pll2_tun; /* 0x0c pll2 tuning */
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u32 pll3_cfg; /* 0x10 pll3 control */
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u8 res0[0x4];
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u32 pll4_cfg; /* 0x18 pll4 control */
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u8 res1[0x4];
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u32 pll5_cfg; /* 0x20 pll5 control */
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u32 pll5_tun; /* 0x24 pll5 tuning */
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u32 pll6_cfg; /* 0x28 pll6 control */
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u32 pll6_tun; /* 0x2c pll6 tuning */
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u32 pll7_cfg; /* 0x30 pll7 control */
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u32 pll1_tun2; /* 0x34 pll5 tuning2 */
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u8 res2[0x4];
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u32 pll5_tun2; /* 0x3c pll5 tuning2 */
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u8 res3[0xc];
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u32 pll_lock_dbg; /* 0x4c pll lock time debug */
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u32 osc24m_cfg; /* 0x50 osc24m control */
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u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */
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u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */
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u32 axi_gate; /* 0x5c axi module clock gating */
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u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
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u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
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u32 apb0_gate; /* 0x68 apb0 module clock gating */
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u32 apb1_gate; /* 0x6c apb1 module clock gating */
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u8 res4[0x10];
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u32 nand_sclk_cfg; /* 0x80 nand sub clock control */
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u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */
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u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
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u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
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u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
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u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
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u32 ts_clk_cfg; /* 0x98 transport stream clock control */
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u32 ss_clk_cfg; /* 0x9c */
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u32 spi0_clk_cfg; /* 0xa0 */
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u32 spi1_clk_cfg; /* 0xa4 */
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u32 spi2_clk_cfg; /* 0xa8 */
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u32 pata_clk_cfg; /* 0xac */
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u32 ir0_clk_cfg; /* 0xb0 */
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u32 ir1_clk_cfg; /* 0xb4 */
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u32 iis_clk_cfg; /* 0xb8 */
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u32 ac97_clk_cfg; /* 0xbc */
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u32 spdif_clk_cfg; /* 0xc0 */
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u32 keypad_clk_cfg; /* 0xc4 */
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u32 sata_clk_cfg; /* 0xc8 */
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u32 usb_clk_cfg; /* 0xcc */
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u32 gps_clk_cfg; /* 0xd0 */
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u32 spi3_clk_cfg; /* 0xd4 */
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u8 res5[0x28];
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u32 dram_clk_cfg; /* 0x100 */
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u32 be0_clk_cfg; /* 0x104 */
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u32 be1_clk_cfg; /* 0x108 */
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u32 fe0_clk_cfg; /* 0x10c */
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u32 fe1_clk_cfg; /* 0x110 */
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u32 mp_clk_cfg; /* 0x114 */
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u32 lcd0_ch0_clk_cfg; /* 0x118 */
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u32 lcd1_ch0_clk_cfg; /* 0x11c */
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u32 csi_isp_clk_cfg; /* 0x120 */
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u8 res6[0x4];
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u32 tvd_clk_reg; /* 0x128 */
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u32 lcd0_ch1_clk_cfg; /* 0x12c */
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u32 lcd1_ch1_clk_cfg; /* 0x130 */
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u32 csi0_clk_cfg; /* 0x134 */
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u32 csi1_clk_cfg; /* 0x138 */
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u32 ve_clk_cfg; /* 0x13c */
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u32 audio_codec_clk_cfg; /* 0x140 */
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u32 avs_clk_cfg; /* 0x144 */
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u32 ace_clk_cfg; /* 0x148 */
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u32 lvds_clk_cfg; /* 0x14c */
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u32 hdmi_clk_cfg; /* 0x150 */
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u32 mali_clk_cfg; /* 0x154 */
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u8 res7[0x4];
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u32 mbus_clk_cfg; /* 0x15c */
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u8 res8[0x4];
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u32 gmac_clk_cfg; /* 0x164 */
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};
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/* apb1 bit field */
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#define APB1_CLK_SRC_OSC24M (0x0 << 24)
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#define APB1_CLK_SRC_PLL6 (0x1 << 24)
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#define APB1_CLK_SRC_LOSC (0x2 << 24)
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#define APB1_CLK_SRC_MASK (0x3 << 24)
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#define APB1_CLK_RATE_N_1 (0x0 << 16)
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#define APB1_CLK_RATE_N_2 (0x1 << 16)
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#define APB1_CLK_RATE_N_4 (0x2 << 16)
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#define APB1_CLK_RATE_N_8 (0x3 << 16)
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#define APB1_CLK_RATE_N_MASK (3 << 16)
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#define APB1_CLK_RATE_M(m) (((m)-1) << 0)
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#define APB1_CLK_RATE_M_MASK (0x1f << 0)
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/* apb1 gate field */
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#define APB1_GATE_UART_SHIFT (16)
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#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT)
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#define APB1_GATE_TWI_SHIFT (0)
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#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT)
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/* clock divide */
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#define AXI_DIV_SHIFT (0)
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#define AXI_DIV_1 0
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#define AXI_DIV_2 1
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#define AXI_DIV_3 2
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#define AXI_DIV_4 3
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#define AHB_DIV_SHIFT (4)
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#define AHB_DIV_1 0
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#define AHB_DIV_2 1
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#define AHB_DIV_4 2
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#define AHB_DIV_8 3
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#define APB0_DIV_SHIFT (8)
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#define APB0_DIV_1 0
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#define APB0_DIV_2 1
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#define APB0_DIV_4 2
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#define APB0_DIV_8 3
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#define CPU_CLK_SRC_SHIFT (16)
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#define CPU_CLK_SRC_OSC24M 1
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#define CPU_CLK_SRC_PLL1 2
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#define CCM_PLL1_CFG_ENABLE_SHIFT 31
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#define CCM_PLL1_CFG_VCO_RST_SHIFT 30
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#define CCM_PLL1_CFG_VCO_BIAS_SHIFT 26
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#define CCM_PLL1_CFG_PLL4_EXCH_SHIFT 25
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#define CCM_PLL1_CFG_BIAS_CUR_SHIFT 20
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#define CCM_PLL1_CFG_DIVP_SHIFT 16
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#define CCM_PLL1_CFG_LCK_TMR_SHIFT 13
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#define CCM_PLL1_CFG_FACTOR_N_SHIFT 8
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#define CCM_PLL1_CFG_FACTOR_K_SHIFT 4
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#define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT 3
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#define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT 2
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#define CCM_PLL1_CFG_FACTOR_M_SHIFT 0
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#define PLL1_CFG_DEFAULT 0xa1005000
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#define PLL6_CFG_DEFAULT 0xa1009911
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/* nand clock */
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#define NAND_CLK_SRC_OSC24 0
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#define NAND_CLK_DIV_N 0
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#define NAND_CLK_DIV_M 0
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/* gps clock */
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#define GPS_SCLK_GATING_OFF 0
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#define GPS_RESET 0
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/* ahb clock gate bit offset */
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#define AHB_GATE_OFFSET_GPS 26
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#define AHB_GATE_OFFSET_SATA 25
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#define AHB_GATE_OFFSET_PATA 24
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#define AHB_GATE_OFFSET_SPI3 23
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#define AHB_GATE_OFFSET_SPI2 22
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#define AHB_GATE_OFFSET_SPI1 21
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#define AHB_GATE_OFFSET_SPI0 20
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#define AHB_GATE_OFFSET_TS0 18
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#define AHB_GATE_OFFSET_EMAC 17
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#define AHB_GATE_OFFSET_ACE 16
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#define AHB_GATE_OFFSET_DLL 15
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#define AHB_GATE_OFFSET_SDRAM 14
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#define AHB_GATE_OFFSET_NAND 13
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#define AHB_GATE_OFFSET_MS 12
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#define AHB_GATE_OFFSET_MMC3 11
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#define AHB_GATE_OFFSET_MMC2 10
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#define AHB_GATE_OFFSET_MMC1 9
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#define AHB_GATE_OFFSET_MMC0 8
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#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
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#define AHB_GATE_OFFSET_BIST 7
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#define AHB_GATE_OFFSET_DMA 6
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#define AHB_GATE_OFFSET_SS 5
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#define AHB_GATE_OFFSET_USB_OHCI1 4
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#define AHB_GATE_OFFSET_USB_EHCI1 3
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#define AHB_GATE_OFFSET_USB_OHCI0 2
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#define AHB_GATE_OFFSET_USB_EHCI0 1
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#define AHB_GATE_OFFSET_USB 0
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/* ahb clock gate bit offset (second register) */
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#define AHB_GATE_OFFSET_GMAC 17
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#define CCM_AHB_GATE_GPS (0x1 << 26)
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#define CCM_AHB_GATE_SDRAM (0x1 << 14)
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#define CCM_AHB_GATE_DLL (0x1 << 15)
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#define CCM_AHB_GATE_ACE (0x1 << 16)
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#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0)
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#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3)
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#define CCM_PLL5_CTRL_M_X(n) ((n) - 1)
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#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2)
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#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3)
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#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1)
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#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4)
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#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3)
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#define CCM_PLL5_CTRL_K_X(n) ((n) - 1)
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#define CCM_PLL5_CTRL_LDO (0x1 << 7)
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#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8)
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#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f)
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#define CCM_PLL5_CTRL_N_X(n) (n)
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#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16)
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#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3)
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#define CCM_PLL5_CTRL_P_X(n) ((n) - 1)
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#define CCM_PLL5_CTRL_BW (0x1 << 18)
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#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19)
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#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20)
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#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f)
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#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1)
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#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25)
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#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29)
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#define CCM_PLL5_CTRL_BYPASS (0x1 << 30)
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#define CCM_PLL5_CTRL_EN (0x1 << 31)
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#define CCM_PLL6_CTRL_N_SHIFT 8
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#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
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#define CCM_PLL6_CTRL_K_SHIFT 4
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#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
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#define CCM_GPS_CTRL_RESET (0x1 << 0)
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#define CCM_GPS_CTRL_GATE (0x1 << 1)
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#define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15)
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#define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0)
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#define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf)
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#define CCM_MBUS_CTRL_M_X(n) ((n) - 1)
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#define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16)
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#define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf)
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#define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0)))
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#define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24)
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#define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3)
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#define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0
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#define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1
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#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
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#define CCM_MBUS_CTRL_GATE (0x1 << 31)
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#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
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#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
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#define CCM_MMC_CTRL_PLL5 (0x2 << 24)
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#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
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#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
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#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
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#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
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#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
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#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
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#endif /* _SUNXI_CLOCK_SUN4I_H */
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