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Gabor Juhos da84f33b04 MIPS: mips32/cache.S: remove superfluous register assignment 
The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.

Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
2013-07-24 09:51:05 -04:00
..
cpu MIPS: mips32/cache.S: remove superfluous register assignment 2013-07-24 09:51:05 -04:00
include/asm MIPS: qemu-malta: setup GT64120 registers as done by YAMON 2013-07-24 09:51:04 -04:00
lib Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
config.mk Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00