mirror of
https://github.com/AsahiLinux/u-boot
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61af2af3f7
As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini <trini@konsulko.com>
498 lines
11 KiB
C
498 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* SMSC LAN9[12]1[567] Network driver
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*/
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <net.h>
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#include <miiphy.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include "smc911x.h"
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struct chip_id {
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u16 id;
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char *name;
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};
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struct smc911x_priv {
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phys_addr_t iobase;
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const struct chip_id *chipid;
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unsigned char enetaddr[6];
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bool use_32_bit_io;
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};
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static const struct chip_id chip_ids[] = {
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{ CHIP_89218, "LAN89218" },
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{ CHIP_9115, "LAN9115" },
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{ CHIP_9116, "LAN9116" },
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{ CHIP_9117, "LAN9117" },
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{ CHIP_9118, "LAN9118" },
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{ CHIP_9211, "LAN9211" },
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{ CHIP_9215, "LAN9215" },
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{ CHIP_9216, "LAN9216" },
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{ CHIP_9217, "LAN9217" },
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{ CHIP_9218, "LAN9218" },
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{ CHIP_9220, "LAN9220" },
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{ CHIP_9221, "LAN9221" },
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{ 0, NULL },
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};
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#define DRIVERNAME "smc911x"
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static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
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{
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if (priv->use_32_bit_io)
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return readl(priv->iobase + offset);
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return (readw(priv->iobase + offset) & 0xffff) |
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(readw(priv->iobase + offset + 2) << 16);
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}
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static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
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{
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if (priv->use_32_bit_io) {
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writel(val, priv->iobase + offset);
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} else {
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writew(val & 0xffff, priv->iobase + offset);
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writew(val >> 16, priv->iobase + offset + 2);
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}
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}
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static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg)
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{
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while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
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;
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smc911x_reg_write(priv, MAC_CSR_CMD,
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MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
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while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
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;
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return smc911x_reg_read(priv, MAC_CSR_DATA);
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}
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static void smc911x_set_mac_csr(struct smc911x_priv *priv, u8 reg, u32 data)
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{
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while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
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;
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smc911x_reg_write(priv, MAC_CSR_DATA, data);
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smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
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while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
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;
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}
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static int smc911x_detect_chip(struct smc911x_priv *priv)
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{
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unsigned long val, i;
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val = smc911x_reg_read(priv, BYTE_TEST);
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if (val == 0xffffffff) {
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/* Special case -- no chip present */
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return -1;
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} else if (val != 0x87654321) {
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printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
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return -1;
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}
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val = smc911x_reg_read(priv, ID_REV) >> 16;
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for (i = 0; chip_ids[i].id != 0; i++) {
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if (chip_ids[i].id == val) break;
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}
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if (!chip_ids[i].id) {
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printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
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return -1;
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}
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priv->chipid = &chip_ids[i];
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return 0;
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}
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static void smc911x_reset(struct smc911x_priv *priv)
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{
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int timeout;
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/*
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* Take out of PM setting first
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* Device is already wake up if PMT_CTRL_READY bit is set
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*/
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if ((smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY) == 0) {
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/* Write to the bytetest will take out of powerdown */
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smc911x_reg_write(priv, BYTE_TEST, 0x0);
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timeout = 10;
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while (timeout-- &&
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!(smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY))
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udelay(10);
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if (timeout < 0) {
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printf(DRIVERNAME
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": timeout waiting for PM restore\n");
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return;
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}
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}
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/* Disable interrupts */
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smc911x_reg_write(priv, INT_EN, 0);
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smc911x_reg_write(priv, HW_CFG, HW_CFG_SRST);
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timeout = 1000;
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while (timeout-- && smc911x_reg_read(priv, E2P_CMD) & E2P_CMD_EPC_BUSY)
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udelay(10);
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if (timeout < 0) {
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printf(DRIVERNAME ": reset timeout\n");
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return;
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}
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/* Reset the FIFO level and flow control settings */
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smc911x_set_mac_csr(priv, FLOW, FLOW_FCPT | FLOW_FCEN);
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smc911x_reg_write(priv, AFC_CFG, 0x0050287F);
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/* Set to LED outputs */
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smc911x_reg_write(priv, GPIO_CFG, 0x70070000);
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}
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static void smc911x_handle_mac_address(struct smc911x_priv *priv)
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{
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unsigned long addrh, addrl;
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unsigned char *m = priv->enetaddr;
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addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
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addrh = m[4] | (m[5] << 8);
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smc911x_set_mac_csr(priv, ADDRL, addrl);
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smc911x_set_mac_csr(priv, ADDRH, addrh);
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printf(DRIVERNAME ": MAC %pM\n", m);
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}
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static bool smc911x_read_mac_address(struct smc911x_priv *priv)
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{
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u32 addrh, addrl;
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/* address is obtained from optional eeprom */
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addrh = smc911x_get_mac_csr(priv, ADDRH);
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addrl = smc911x_get_mac_csr(priv, ADDRL);
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if (addrl == 0xffffffff && addrh == 0x0000ffff)
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return false;
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priv->enetaddr[0] = addrl;
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priv->enetaddr[1] = addrl >> 8;
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priv->enetaddr[2] = addrl >> 16;
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priv->enetaddr[3] = addrl >> 24;
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priv->enetaddr[4] = addrh;
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priv->enetaddr[5] = addrh >> 8;
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return true;
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}
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static int smc911x_eth_phy_read(struct smc911x_priv *priv,
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u8 phy, u8 reg, u16 *val)
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{
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while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
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;
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smc911x_set_mac_csr(priv, MII_ACC, phy << 11 | reg << 6 |
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MII_ACC_MII_BUSY);
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while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
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;
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*val = smc911x_get_mac_csr(priv, MII_DATA);
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return 0;
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}
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static int smc911x_eth_phy_write(struct smc911x_priv *priv,
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u8 phy, u8 reg, u16 val)
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{
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while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
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;
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smc911x_set_mac_csr(priv, MII_DATA, val);
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smc911x_set_mac_csr(priv, MII_ACC,
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phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
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while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
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;
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return 0;
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}
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static int smc911x_phy_reset(struct smc911x_priv *priv)
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{
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u32 reg;
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reg = smc911x_reg_read(priv, PMT_CTRL);
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reg &= ~0xfffff030;
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reg |= PMT_CTRL_PHY_RST;
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smc911x_reg_write(priv, PMT_CTRL, reg);
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mdelay(100);
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return 0;
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}
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static void smc911x_phy_configure(struct smc911x_priv *priv)
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{
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int timeout;
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u16 status;
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smc911x_phy_reset(priv);
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smc911x_eth_phy_write(priv, 1, MII_BMCR, BMCR_RESET);
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mdelay(1);
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smc911x_eth_phy_write(priv, 1, MII_ADVERTISE, 0x01e1);
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smc911x_eth_phy_write(priv, 1, MII_BMCR, BMCR_ANENABLE |
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BMCR_ANRESTART);
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timeout = 5000;
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do {
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mdelay(1);
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if ((timeout--) == 0)
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goto err_out;
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if (smc911x_eth_phy_read(priv, 1, MII_BMSR, &status) != 0)
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goto err_out;
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} while (!(status & BMSR_LSTATUS));
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printf(DRIVERNAME ": phy initialized\n");
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return;
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err_out:
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printf(DRIVERNAME ": autonegotiation timed out\n");
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}
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static void smc911x_enable(struct smc911x_priv *priv)
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{
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/* Enable TX */
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smc911x_reg_write(priv, HW_CFG, 8 << 16 | HW_CFG_SF);
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smc911x_reg_write(priv, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
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smc911x_reg_write(priv, TX_CFG, TX_CFG_TX_ON);
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/* no padding to start of packets */
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smc911x_reg_write(priv, RX_CFG, 0);
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smc911x_set_mac_csr(priv, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
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MAC_CR_HBDIS);
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}
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static int smc911x_init_common(struct smc911x_priv *priv)
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{
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const struct chip_id *id = priv->chipid;
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printf(DRIVERNAME ": detected %s controller\n", id->name);
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smc911x_reset(priv);
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/* Configure the PHY, initialize the link state */
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smc911x_phy_configure(priv);
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smc911x_handle_mac_address(priv);
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/* Turn on Tx + Rx */
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smc911x_enable(priv);
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return 0;
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}
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static int smc911x_send_common(struct smc911x_priv *priv,
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void *packet, int length)
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{
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u32 *data = (u32*)packet;
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u32 tmplen;
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u32 status;
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smc911x_reg_write(priv, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG |
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TX_CMD_A_INT_LAST_SEG | length);
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smc911x_reg_write(priv, TX_DATA_FIFO, length);
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tmplen = (length + 3) / 4;
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while (tmplen--)
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smc911x_reg_write(priv, TX_DATA_FIFO, *data++);
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/* wait for transmission */
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while (!((smc911x_reg_read(priv, TX_FIFO_INF) &
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TX_FIFO_INF_TSUSED) >> 16));
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/* get status. Ignore 'no carrier' error, it has no meaning for
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* full duplex operation
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*/
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status = smc911x_reg_read(priv, TX_STATUS_FIFO) &
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(TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
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TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
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if (!status)
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return 0;
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printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
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status & TX_STS_LOC ? "TX_STS_LOC " : "",
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status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
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status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
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status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
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status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
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return -1;
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}
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static void smc911x_halt_common(struct smc911x_priv *priv)
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{
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smc911x_reset(priv);
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smc911x_handle_mac_address(priv);
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}
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static int smc911x_recv_common(struct smc911x_priv *priv, u32 *data)
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{
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u32 pktlen, tmplen;
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u32 status;
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status = smc911x_reg_read(priv, RX_FIFO_INF);
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if (!(status & RX_FIFO_INF_RXSUSED))
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return 0;
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status = smc911x_reg_read(priv, RX_STATUS_FIFO);
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pktlen = (status & RX_STS_PKT_LEN) >> 16;
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smc911x_reg_write(priv, RX_CFG, 0);
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tmplen = (pktlen + 3) / 4;
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while (tmplen--)
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*data++ = smc911x_reg_read(priv, RX_DATA_FIFO);
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if (status & RX_STS_ES) {
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printf(DRIVERNAME
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": dropped bad packet. Status: 0x%08x\n",
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status);
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return 0;
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}
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return pktlen;
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}
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static int smc911x_start(struct udevice *dev)
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{
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struct eth_pdata *plat = dev_get_plat(dev);
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struct smc911x_priv *priv = dev_get_priv(dev);
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memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
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return smc911x_init_common(priv);
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}
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static void smc911x_stop(struct udevice *dev)
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{
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struct smc911x_priv *priv = dev_get_priv(dev);
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smc911x_halt_common(priv);
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}
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static int smc911x_send(struct udevice *dev, void *packet, int length)
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{
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struct smc911x_priv *priv = dev_get_priv(dev);
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int ret;
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ret = smc911x_send_common(priv, packet, length);
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return ret ? 0 : -ETIMEDOUT;
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}
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static int smc911x_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct smc911x_priv *priv = dev_get_priv(dev);
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u32 *data = (u32 *)net_rx_packets[0];
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int ret;
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ret = smc911x_recv_common(priv, data);
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if (ret)
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*packetp = (void *)data;
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return ret ? ret : -EAGAIN;
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}
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static int smc911x_read_rom_hwaddr(struct udevice *dev)
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{
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struct smc911x_priv *priv = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_plat(dev);
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if (!smc911x_read_mac_address(priv))
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return -ENODEV;
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memcpy(pdata->enetaddr, priv->enetaddr, sizeof(pdata->enetaddr));
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return 0;
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}
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static int smc911x_bind(struct udevice *dev)
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{
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return device_set_name(dev, dev->name);
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}
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static int smc911x_probe(struct udevice *dev)
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{
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struct smc911x_priv *priv = dev_get_priv(dev);
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int ret;
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/* Try to detect chip. Will fail if not present. */
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ret = smc911x_detect_chip(priv);
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if (ret)
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return ret;
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smc911x_read_rom_hwaddr(dev);
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return 0;
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}
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static int smc911x_of_to_plat(struct udevice *dev)
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{
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struct smc911x_priv *priv = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_plat(dev);
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u32 io_width;
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int ret;
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pdata->iobase = dev_read_addr(dev);
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priv->iobase = pdata->iobase;
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ret = dev_read_u32(dev, "reg-io-width", &io_width);
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if (!ret)
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priv->use_32_bit_io = (io_width == 4);
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else
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priv->use_32_bit_io = CONFIG_IS_ENABLED(SMC911X_32_BIT);
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return 0;
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}
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static const struct eth_ops smc911x_ops = {
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.start = smc911x_start,
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.send = smc911x_send,
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.recv = smc911x_recv,
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.stop = smc911x_stop,
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.read_rom_hwaddr = smc911x_read_rom_hwaddr,
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};
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static const struct udevice_id smc911x_ids[] = {
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{ .compatible = "smsc,lan9115" },
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{ }
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};
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U_BOOT_DRIVER(smc911x) = {
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.name = "eth_smc911x",
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.id = UCLASS_ETH,
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.of_match = smc911x_ids,
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.bind = smc911x_bind,
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|
.of_to_plat = smc911x_of_to_plat,
|
|
.probe = smc911x_probe,
|
|
.ops = &smc911x_ops,
|
|
.priv_auto = sizeof(struct smc911x_priv),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|