mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2817 lines
165 KiB
C
2817 lines
165 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* Author:
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* Peng Fan <Peng.Fan@freescale.com>
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*/
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#ifndef __ARCH_ARM_MACH_MX7_CCM_REGS_H__
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#define __ARCH_ARM_MACH_MX7_CCM_REGS_H__
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#include <asm/arch/imx-regs.h>
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#include <asm/io.h>
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#define CCM_GPR0_OFFSET 0x0
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#define CCM_OBSERVE0_OFFSET 0x0400
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#define CCM_SCTRL0_OFFSET 0x0800
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#define CCM_CCGR0_OFFSET 0x4000
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#define CCM_ROOT0_TARGET_OFFSET 0x8000
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#ifndef __ASSEMBLY__
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struct mxc_ccm_ccgr {
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uint32_t ccgr;
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uint32_t ccgr_set;
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uint32_t ccgr_clr;
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uint32_t ccgr_tog;
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};
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struct mxc_ccm_root_slice {
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uint32_t target_root;
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uint32_t target_root_set;
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uint32_t target_root_clr;
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uint32_t target_root_tog;
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uint32_t reserved_0[4];
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uint32_t post;
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uint32_t post_root_set;
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uint32_t post_root_clr;
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uint32_t post_root_tog;
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uint32_t pre;
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uint32_t pre_root_set;
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uint32_t pre_root_clr;
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uint32_t pre_root_tog;
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uint32_t reserved_1[12];
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uint32_t access_ctrl;
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uint32_t access_ctrl_root_set;
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uint32_t access_ctrl_root_clr;
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uint32_t access_ctrl_root_tog;
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};
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/** CCM - Peripheral register structure */
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struct mxc_ccm_reg {
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uint32_t gpr0;
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uint32_t gpr0_set;
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uint32_t gpr0_clr;
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uint32_t gpr0_tog;
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uint32_t reserved_0[4092];
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struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */
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uint32_t reserved_1[3332];
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struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */
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};
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struct mxc_ccm_anatop_reg {
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uint32_t ctrl_24m; /* offset 0x0000 */
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uint32_t ctrl_24m_set;
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uint32_t ctrl_24m_clr;
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uint32_t ctrl_24m_tog;
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uint32_t rcosc_config0; /* offset 0x0010 */
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uint32_t rcosc_config0_set;
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uint32_t rcosc_config0_clr;
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uint32_t rcosc_config0_tog;
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uint32_t rcosc_config1; /* offset 0x0020 */
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uint32_t rcosc_config1_set;
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uint32_t rcosc_config1_clr;
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uint32_t rcosc_config1_tog;
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uint32_t rcosc_config2; /* offset 0x0030 */
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uint32_t rcosc_config2_set;
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uint32_t rcosc_config2_clr;
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uint32_t rcosc_config2_tog;
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uint8_t reserved_0[16];
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uint32_t osc_32k; /* offset 0x0050 */
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uint32_t osc_32k_set;
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uint32_t osc_32k_clr;
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uint32_t osc_32k_tog;
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uint32_t pll_arm; /* offset 0x0060 */
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uint32_t pll_arm_set;
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uint32_t pll_arm_clr;
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uint32_t pll_arm_tog;
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uint32_t pll_ddr; /* offset 0x0070 */
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uint32_t pll_ddr_set;
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uint32_t pll_ddr_clr;
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uint32_t pll_ddr_tog;
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uint32_t pll_ddr_ss; /* offset 0x0080 */
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uint8_t reserved_1[12];
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uint32_t pll_ddr_num; /* offset 0x0090 */
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uint8_t reserved_2[12];
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uint32_t pll_ddr_denom; /* offset 0x00a0 */
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uint8_t reserved_3[12];
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uint32_t pll_480; /* offset 0x00b0 */
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uint32_t pll_480_set;
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uint32_t pll_480_clr;
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uint32_t pll_480_tog;
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uint32_t pfd_480a; /* offset 0x00c0 */
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uint32_t pfd_480a_set;
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uint32_t pfd_480a_clr;
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uint32_t pfd_480a_tog;
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uint32_t pfd_480b; /* offset 0x00d0 */
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uint32_t pfd_480b_set;
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uint32_t pfd_480b_clr;
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uint32_t pfd_480b_tog;
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uint32_t pll_enet; /* offset 0x00e0 */
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uint32_t pll_enet_set;
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uint32_t pll_enet_clr;
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uint32_t pll_enet_tog;
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uint32_t pll_audio; /* offset 0x00f0 */
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uint32_t pll_audio_set;
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uint32_t pll_audio_clr;
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uint32_t pll_audio_tog;
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uint32_t pll_audio_ss; /* offset 0x0100 */
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uint8_t reserved_4[12];
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uint32_t pll_audio_num; /* offset 0x0110 */
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uint8_t reserved_5[12];
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uint32_t pll_audio_denom; /* offset 0x0120 */
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uint8_t reserved_6[12];
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uint32_t pll_video; /* offset 0x0130 */
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uint32_t pll_video_set;
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uint32_t pll_video_clr;
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uint32_t pll_video_tog;
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uint32_t pll_video_ss; /* offset 0x0140 */
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uint8_t reserved_7[12];
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uint32_t pll_video_num; /* offset 0x0150 */
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uint8_t reserved_8[12];
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uint32_t pll_video_denom; /* offset 0x0160 */
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uint8_t reserved_9[12];
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uint32_t clk_misc0; /* offset 0x0170 */
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uint32_t clk_misc0_set;
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uint32_t clk_misc0_clr;
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uint32_t clk_misc0_tog;
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uint32_t clk_rsvd; /* offset 0x0180 */
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uint8_t reserved_10[124];
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uint32_t reg_1p0a; /* offset 0x0200 */
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uint32_t reg_1p0a_set;
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uint32_t reg_1p0a_clr;
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uint32_t reg_1p0a_tog;
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uint32_t reg_1p0d; /* offsest 0x0210 */
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uint32_t reg_1p0d_set;
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uint32_t reg_1p0d_clr;
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uint32_t reg_1p0d_tog;
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uint32_t reg_hsic_1p2; /* offset 0x0220 */
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uint32_t reg_hsic_1p2_set;
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uint32_t reg_hsic_1p2_clr;
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uint32_t reg_hsic_1p2_tog;
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uint32_t reg_lpsr_1p0; /* offset 0x0230 */
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uint32_t reg_lpsr_1p0_set;
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uint32_t reg_lpsr_1p0_clr;
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uint32_t reg_lpsr_1p0_tog;
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uint32_t reg_3p0; /* offset 0x0240 */
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uint32_t reg_3p0_set;
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uint32_t reg_3p0_clr;
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uint32_t reg_3p0_tog;
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uint32_t reg_snvs; /* offset 0x0250 */
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uint32_t reg_snvs_set;
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uint32_t reg_snvs_clr;
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uint32_t reg_snvs_tog;
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uint32_t analog_debug_misc0; /* offset 0x0260 */
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uint32_t analog_debug_misc0_set;
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uint32_t analog_debug_misc0_clr;
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uint32_t analog_debug_misc0_tog;
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uint32_t ref; /* offset 0x0270 */
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uint32_t ref_set;
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uint32_t ref_clr;
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uint32_t ref_tog;
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uint8_t reserved_11[128];
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uint32_t tempsense0; /* offset 0x0300 */
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uint32_t tempsense0_set;
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uint32_t tempsense0_clr;
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uint32_t tempsense0_tog;
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uint32_t tempsense1; /* offset 0x0310 */
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uint32_t tempsense1_set;
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uint32_t tempsense1_clr;
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uint32_t tempsense1_tog;
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uint32_t tempsense_trim; /* offset 0x0320 */
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uint32_t tempsense_trim_set;
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uint32_t tempsense_trim_clr;
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uint32_t tempsense_trim_tog;
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uint32_t lowpwr_ctrl; /* offset 0x0330 */
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uint32_t lowpwr_ctrl_set;
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uint32_t lowpwr_ctrl_clr;
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uint32_t lowpwr_ctrl_tog;
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uint32_t snvs_tamper_offset_ctrl; /* offset 0x0340 */
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uint32_t snvs_tamper_offset_ctrl_set;
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uint32_t snvs_tamper_offset_ctrl_clr;
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uint32_t snvs_tamper_offset_ctrl_tog;
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uint32_t snvs_tamper_pull_ctrl; /* offset 0x0350 */
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uint32_t snvs_tamper_pull_ctrl_set;
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uint32_t snvs_tamper_pull_ctrl_clr;
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uint32_t snvs_tamper_pull_ctrl_tog;
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uint32_t snvs_test; /* offset 0x0360 */
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uint32_t snvs_test_set;
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uint32_t snvs_test_clr;
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uint32_t snvs_test_tog;
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uint32_t snvs_tamper_trim_ctrl; /* offset 0x0370 */
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uint32_t snvs_tamper_trim_ctrl_set;
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uint32_t snvs_tamper_trim_ctrl_ctrl;
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uint32_t snvs_tamper_trim_ctrl_tog;
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uint32_t snvs_misc_ctrl; /* offset 0x0380 */
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uint32_t snvs_misc_ctrl_set;
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uint32_t snvs_misc_ctrl_clr;
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uint32_t snvs_misc_ctrl_tog;
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uint8_t reserved_12[112];
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uint32_t misc; /* offset 0x0400 */
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uint8_t reserved_13[252];
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uint32_t adc0; /* offset 0x0500 */
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uint8_t reserved_14[12];
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uint32_t adc1; /* offset 0x0510 */
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uint8_t reserved_15[748];
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uint32_t digprog; /* offset 0x0800 */
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};
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#endif
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#define ANADIG_CLK_MISC0_PFD_480_AUTOGATE_EN_MASK (0x01 << 17)
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#define ANADIG_PLL_LOCK 0x80000000
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#define ANADIG_PLL_ARM_PWDN_MASK (0x01 << 12)
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#define ANADIG_PLL_480_PWDN_MASK (0x01 << 12)
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#define ANADIG_PLL_DDR_PWDN_MASK (0x01 << 20)
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#define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5)
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#define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12)
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#define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f
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#define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B
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#define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016
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#define ANATOP_PFD480B_PFD4_FRAC_432M_VAL 0x00000014
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/* PLL_ARM Bit Fields */
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#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7F
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#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0
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#define CCM_ANALOG_PLL_ARM_HALF_LF_MASK 0x80
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#define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT 7
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#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK 0x100
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#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT 8
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#define CCM_ANALOG_PLL_ARM_HALF_CP_MASK 0x200
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#define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT 9
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#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK 0x400
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#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT 10
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#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK 0x800
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#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT 11
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#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK 0x1000
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#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT 12
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#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK 0x2000
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#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT 13
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#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK 0xC000
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#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT 14
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#define CCM_ANALOG_PLL_ARM_BYPASS_MASK 0x10000
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#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT 16
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#define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK 0x20000
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#define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT 17
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#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK 0x40000
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#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT 18
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#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK 0x80000
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#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT 19
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#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK 0x100000
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#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT 20
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#define CCM_ANALOG_PLL_ARM_RSVD0_MASK 0x7FE00000
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#define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT 21
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#define CCM_ANALOG_PLL_ARM_LOCK_MASK 0x80000000
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#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT 31
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/* PLL_DDR Bit Fields */
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#define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK 0x7F
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#define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT 0
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#define CCM_ANALOG_PLL_DDR_HALF_LF_MASK 0x80
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#define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT 7
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#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK 0x100
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#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT 8
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#define CCM_ANALOG_PLL_DDR_HALF_CP_MASK 0x200
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#define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT 9
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#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK 0x400
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#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT 10
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#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK 0x800
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#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT 11
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#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK 0x1000
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#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT 12
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#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK 0x2000
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#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT 13
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#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK 0xC000
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#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT 14
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#define CCM_ANALOG_PLL_DDR_BYPASS_MASK 0x10000
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#define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT 16
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#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK 0x20000
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#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT 17
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#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK 0x40000
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#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT 18
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#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK 0x80000
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#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT 19
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#define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK 0x100000
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#define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT 20
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#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK 0x600000
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#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT 21
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#define CCM_ANALOG_PLL_DDR_RSVD1_MASK 0x7F800000
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#define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT 23
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#define CCM_ANALOG_PLL_DDR_LOCK_MASK 0x80000000
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#define CCM_ANALOG_PLL_DDR_LOCK_SHIFT 31
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/* PLL_480 Bit Fields */
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#define CCM_ANALOG_PLL_480_DIV_SELECT_MASK 0x1
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#define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT 0
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#define CCM_ANALOG_PLL_480_RSVD0_MASK 0xE
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#define CCM_ANALOG_PLL_480_RSVD0_SHIFT 1
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#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK 0x10
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#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT 4
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#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK 0x20
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#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT 5
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#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK 0x40
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#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT 6
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#define CCM_ANALOG_PLL_480_HALF_LF_MASK 0x80
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#define CCM_ANALOG_PLL_480_HALF_LF_SHIFT 7
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#define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK 0x100
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#define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT 8
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#define CCM_ANALOG_PLL_480_HALF_CP_MASK 0x200
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#define CCM_ANALOG_PLL_480_HALF_CP_SHIFT 9
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#define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK 0x400
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#define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT 10
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#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK 0x800
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#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT 11
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#define CCM_ANALOG_PLL_480_POWERDOWN_MASK 0x1000
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#define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT 12
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#define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK 0x2000
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#define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT 13
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#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK 0xC000
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#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT 14
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#define CCM_ANALOG_PLL_480_BYPASS_MASK 0x10000
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#define CCM_ANALOG_PLL_480_BYPASS_SHIFT 16
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#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK 0x20000
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#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT 17
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#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK 0x40000
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#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT 18
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#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK 0x80000
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#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT 19
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#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK 0x100000
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#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT 20
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#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK 0x200000
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#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT 21
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#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK 0x400000
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#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT 22
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#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK 0x800000
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#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT 23
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#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK 0x1000000
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#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT 24
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#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK 0x2000000
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#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT 25
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#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK 0x4000000
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#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT 26
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#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK 0x8000000
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#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT 27
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#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK 0x10000000
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#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT 28
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#define CCM_ANALOG_PLL_480_RSVD1_MASK 0x60000000
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#define CCM_ANALOG_PLL_480_RSVD1_SHIFT 29
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#define CCM_ANALOG_PLL_480_LOCK_MASK 0x80000000
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#define CCM_ANALOG_PLL_480_LOCK_SHIFT 31
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/* PFD_480A Bit Fields */
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#define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK 0x3F
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#define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT 0
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#define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK 0x40
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#define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT 6
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#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK 0x80
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#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT 7
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#define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK 0x3F00
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#define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT 8
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#define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK 0x4000
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#define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT 14
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#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK 0x8000
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#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT 15
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#define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK 0x3F0000
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#define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT 16
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#define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK 0x400000
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#define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT 22
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#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK 0x800000
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#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT 23
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#define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK 0x3F000000
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#define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT 24
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#define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK 0x40000000
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#define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT 30
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#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK 0x80000000
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#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT 31
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/* PFD_480B Bit Fields */
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#define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK 0x3F
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#define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT 0
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#define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK 0x40
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#define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT 6
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#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK 0x80
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#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT 7
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#define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK 0x3F00
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#define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT 8
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#define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK 0x4000
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#define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT 14
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#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK 0x8000
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#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT 15
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#define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK 0x3F0000
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#define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT 16
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#define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK 0x400000
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#define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT 22
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#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK 0x800000
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#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT 23
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#define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK 0x3F000000
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#define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT 24
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#define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK 0x40000000
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#define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT 30
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#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK 0x80000000
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#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT 31
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/* PLL_ENET Bit Fields */
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#define CCM_ANALOG_PLL_ENET_HALF_LF_MASK 0x1
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#define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT 0
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#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK 0x2
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#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT 1
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#define CCM_ANALOG_PLL_ENET_HALF_CP_MASK 0x4
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#define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT 2
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#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK 0x8
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#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT 3
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#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK 0x10
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#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT 4
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#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK 0x20
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#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT 5
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK 0x40
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT 6
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 0x80
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT 7
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 0x100
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT 8
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 0x200
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT 9
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 0x400
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT 10
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 0x800
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT 11
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 0x1000
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#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT 12
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#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK 0x2000
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#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT 13
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#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK 0xC000
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#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14
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#define CCM_ANALOG_PLL_ENET_BYPASS_MASK 0x10000
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#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT 16
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#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK 0x20000
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#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT 17
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#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK 0x40000
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#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT 18
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#define CCM_ANALOG_PLL_ENET_RSVD1_MASK 0x7FF80000
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#define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT 19
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#define CCM_ANALOG_PLL_ENET_LOCK_MASK 0x80000000
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#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT 31
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/* PLL_AUDIO Bit Fields */
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#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK 0x7Fu
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#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT 0
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#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK 0x80u
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#define CCM_ANALOG_PLL_AUDIO_HALF_LF_SHIFT 7
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#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK 0x100u
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#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_SHIFT 8
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#define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK 0x200u
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#define CCM_ANALOG_PLL_AUDIO_HALF_CP_SHIFT 9
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#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK 0x400u
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#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_SHIFT 10
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#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK 0x800u
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#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_SHIFT 11
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#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK 0x1000u
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#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT 12
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#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK 0x2000u
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#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT 13
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#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u
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#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14
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#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK 0x10000u
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#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT 16
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#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK 0x20000u
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#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_SHIFT 17
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#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK 0x40000u
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#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18
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#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u
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#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT 19
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#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK 0x200000u
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#define CCM_ANALOG_PLL_AUDIO_RSVD0_SHIFT 21
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#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK 0xC00000u
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#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT 22
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#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK)
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#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
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#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_SHIFT 24
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#define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK 0x7E000000u
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#define CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT 25
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#define CCM_ANALOG_PLL_AUDIO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_RSVD1_MASK)
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#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK 0x80000000u
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#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT 31
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/* PLL_AUDIO_SET Bit Fields */
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#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu
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#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0
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#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK 0x80u
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#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_SHIFT 7
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#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK 0x100u
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#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_SHIFT 8
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#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK 0x200u
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#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_SHIFT 9
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#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK 0x400u
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#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_SHIFT 10
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#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u
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#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_SHIFT 11
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#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK 0x1000u
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#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12
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#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u
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#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_SHIFT 13
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#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u
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#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14
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#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK 0x10000u
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#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT 16
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#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u
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#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_SHIFT 17
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#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u
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#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18
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#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u
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#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT 19
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#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK 0x200000u
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#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_SHIFT 21
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#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u
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#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT 22
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#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
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#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_SHIFT 24
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#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK 0x7E000000u
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#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT 25
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#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK 0x80000000u
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#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT 31
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/* PLL_AUDIO_CLR Bit Fields */
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#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu
|
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#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0
|
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#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK 0x80u
|
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#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_SHIFT 7
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#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK 0x100u
|
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#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_SHIFT 8
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#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK 0x200u
|
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#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_SHIFT 9
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#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK 0x400u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_SHIFT 10
|
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#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_SHIFT 11
|
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#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK 0x1000u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12
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#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_SHIFT 13
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#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14
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|
#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK 0x10000u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT 16
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#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_SHIFT 17
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|
#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18
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#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT 19
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|
#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK 0x200000u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_SHIFT 21
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT 22
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|
#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK)
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#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_SHIFT 24
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK 0x7E000000u
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT 25
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#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK)
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#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK 0x80000000u
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#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT 31
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/* PLL_AUDIO_TOG Bit Fields */
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#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu
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#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0
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#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK 0x80u
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#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_SHIFT 7
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#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK 0x100u
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#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_SHIFT 8
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#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK 0x200u
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#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_SHIFT 9
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#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK 0x400u
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#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_SHIFT 10
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#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u
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#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_SHIFT 11
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#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK 0x1000u
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#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12
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#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u
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#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_SHIFT 13
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#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
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#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14
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#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK 0x10000u
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#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT 16
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#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u
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#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_SHIFT 17
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#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u
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#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18
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#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u
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#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT 19
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#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK 0x200000u
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#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_SHIFT 21
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#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u
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#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT 22
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#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK)
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#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
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#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_SHIFT 24
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#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK 0x7E000000u
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#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT 25
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#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK)
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#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK 0x80000000u
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#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT 31
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/* PLL_AUDIO_SS Bit Fields */
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#define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK 0x7FFFu
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#define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT 0
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#define CCM_ANALOG_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK 0x8000u
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#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_SHIFT 15
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#define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK 0xFFFF0000u
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#define CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT 16
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#define CCM_ANALOG_PLL_AUDIO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK)
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/* PLL_AUDIO_NUM Bit Fields */
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#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK 0x3FFFFFFFu
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#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT 0
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#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
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#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK 0xC0000000u
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#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT 30
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#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK)
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/* PLL_AUDIO_DENOM Bit Fields */
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#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK 0x3FFFFFFFu
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#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT 0
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#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
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#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK 0xC0000000u
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#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT 30
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#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK)
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/* PLL_VIDEO Bit Fields */
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#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK 0x7Fu
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#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT 0
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#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK 0x80u
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#define CCM_ANALOG_PLL_VIDEO_HALF_LF_SHIFT 7
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#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK 0x100u
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#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_SHIFT 8
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#define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK 0x200u
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#define CCM_ANALOG_PLL_VIDEO_HALF_CP_SHIFT 9
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#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK 0x400u
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#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_SHIFT 10
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#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK 0x800u
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#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_SHIFT 11
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#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK 0x1000u
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#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT 12
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#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK 0x2000u
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#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT 13
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#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u
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#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14
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#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK 0x10000u
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#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT 16
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#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK 0x20000u
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#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_SHIFT 17
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#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK 0x40000u
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#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18
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#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u
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#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT 19
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#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK 0x200000u
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#define CCM_ANALOG_PLL_VIDEO_RSVD0_SHIFT 21
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#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK 0xC00000u
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#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT 22
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#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK)
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#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
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#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_SHIFT 24
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#define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK 0x7E000000u
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#define CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT 25
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#define CCM_ANALOG_PLL_VIDEO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_RSVD1_MASK)
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#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK 0x80000000u
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#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT 31
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/* PLL_VIDEO_SET Bit Fields */
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#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu
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#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0
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#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK 0x80u
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#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_SHIFT 7
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#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK 0x100u
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#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_SHIFT 8
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#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK 0x200u
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#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_SHIFT 9
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#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK 0x400u
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#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_SHIFT 10
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#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u
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#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_SHIFT 11
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#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK 0x1000u
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#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12
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#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u
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#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_SHIFT 13
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#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u
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#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14
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#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK 0x10000u
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#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT 16
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#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u
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#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_SHIFT 17
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#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u
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#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18
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#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u
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#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT 19
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#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK 0x200000u
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#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_SHIFT 21
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#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u
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#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT 22
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#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
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#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_SHIFT 24
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#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK 0x7E000000u
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#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT 25
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#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK 0x80000000u
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#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT 31
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/* PLL_VIDEO_CLR Bit Fields */
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#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu
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#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0
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#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK 0x80u
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#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_SHIFT 7
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#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK 0x100u
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#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_SHIFT 8
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#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK 0x200u
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#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_SHIFT 9
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#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK 0x400u
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#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_SHIFT 10
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#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u
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#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_SHIFT 11
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#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK 0x1000u
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#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12
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#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u
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#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_SHIFT 13
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#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
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#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14
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#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK 0x10000u
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#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT 16
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#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u
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#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_SHIFT 17
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#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u
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#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18
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#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u
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#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT 19
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#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK 0x200000u
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#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_SHIFT 21
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#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u
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#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT 22
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#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK)
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#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
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#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_SHIFT 24
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#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK 0x7E000000u
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#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT 25
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#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK)
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#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK 0x80000000u
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#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT 31
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/* PLL_VIDEO_TOG Bit Fields */
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#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu
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#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0
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#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK 0x80u
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#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_SHIFT 7
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#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK 0x100u
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#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_SHIFT 8
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#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK 0x200u
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#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_SHIFT 9
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#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK 0x400u
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#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_SHIFT 10
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#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u
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#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_SHIFT 11
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#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK 0x1000u
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#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12
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#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u
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#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_SHIFT 13
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#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
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#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14
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#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK 0x10000u
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#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT 16
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#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u
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#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_SHIFT 17
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#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u
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#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18
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#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u
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#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT 19
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#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK 0x200000u
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#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_SHIFT 21
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#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u
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#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT 22
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#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK)
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#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
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#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_SHIFT 24
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#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK 0x7E000000u
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#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT 25
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#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK)
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#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK 0x80000000u
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#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT 31
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/* PLL_VIDEO_SS Bit Fields */
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#define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK 0x7FFFu
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#define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT 0
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#define CCM_ANALOG_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK 0x8000u
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#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_SHIFT 15
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#define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK 0xFFFF0000u
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#define CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT 16
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#define CCM_ANALOG_PLL_VIDEO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK)
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/* PLL_VIDEO_NUM Bit Fields */
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#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK 0x3FFFFFFFu
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#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT 0
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#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
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#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK 0xC0000000u
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#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT 30
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#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK)
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/* PLL_VIDEO_DENOM Bit Fields */
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#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK 0x3FFFFFFFu
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#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT 0
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#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
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#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK 0xC0000000u
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#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT 30
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#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK)
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/* CLK_MISC0 Bit Fields */
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#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK 0x1Fu
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#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0
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#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK)
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#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK 0x20u
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#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_SHIFT 5
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#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK 0x40u
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#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_SHIFT 6
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#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK 0x80u
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#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_SHIFT 7
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#define CCM_ANALOG_CLK_MISC0_RSVD0_MASK 0xFFFFFF00u
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#define CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT 8
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#define CCM_ANALOG_CLK_MISC0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_RSVD0_MASK)
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/* CLK_MISC0_SET Bit Fields */
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#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu
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#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0
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#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK)
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#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u
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#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_SHIFT 5
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#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u
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#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_SHIFT 6
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#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u
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#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_SHIFT 7
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#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK 0xFFFFFF00u
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#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT 8
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#define CCM_ANALOG_CLK_MISC0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK)
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/* CLK_MISC0_CLR Bit Fields */
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#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu
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#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0
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#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK)
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#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u
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#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_SHIFT 5
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#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u
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#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_SHIFT 6
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#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u
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#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_SHIFT 7
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#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK 0xFFFFFF00u
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#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT 8
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#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK)
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/* CLK_MISC0_TOG Bit Fields */
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#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu
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#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0
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#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK)
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#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u
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#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_SHIFT 5
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#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u
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#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_SHIFT 6
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#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u
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#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_SHIFT 7
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#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK 0xFFFFFF00u
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#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT 8
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#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK)
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/* REG_1P0A Bit Fields */
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#define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u
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#define PMU_REG_1P0A_ENABLE_BO_SHIFT 1
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#define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u
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#define PMU_REG_1P0A_BO_OFFSET_SHIFT 4
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#define PMU_REG_1P0A_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_BO_OFFSET_SHIFT))&PMU_REG_1P0A_BO_OFFSET_MASK)
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#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_1P0A_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_1P0A_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_1P0A_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_OUTPUT_TRG_MASK)
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#define PMU_REG_1P0A_RSVD0_MASK 0xE000u
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#define PMU_REG_1P0A_RSVD0_SHIFT 13
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#define PMU_REG_1P0A_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD0_SHIFT))&PMU_REG_1P0A_RSVD0_MASK)
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#define PMU_REG_1P0A_BO_MASK 0x10000u
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#define PMU_REG_1P0A_BO_SHIFT 16
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#define PMU_REG_1P0A_OK_MASK 0x20000u
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#define PMU_REG_1P0A_OK_SHIFT 17
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#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_1P0A_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_1P0A_REG_TEST_MASK 0xF00000u
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#define PMU_REG_1P0A_REG_TEST_SHIFT 20
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#define PMU_REG_1P0A_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_REG_TEST_SHIFT))&PMU_REG_1P0A_REG_TEST_MASK)
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#define PMU_REG_1P0A_RSVD1_MASK 0xFF000000u
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#define PMU_REG_1P0A_RSVD1_SHIFT 24
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#define PMU_REG_1P0A_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD1_SHIFT))&PMU_REG_1P0A_RSVD1_MASK)
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/* REG_1P0A_SET Bit Fields */
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#define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_1P0A_SET_ENABLE_BO_MASK 0x2u
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#define PMU_REG_1P0A_SET_ENABLE_BO_SHIFT 1
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#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_1P0A_SET_BO_OFFSET_MASK 0x70u
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#define PMU_REG_1P0A_SET_BO_OFFSET_SHIFT 4
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#define PMU_REG_1P0A_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0A_SET_BO_OFFSET_MASK)
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#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_1P0A_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_SET_OUTPUT_TRG_MASK)
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#define PMU_REG_1P0A_SET_RSVD0_MASK 0xE000u
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#define PMU_REG_1P0A_SET_RSVD0_SHIFT 13
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#define PMU_REG_1P0A_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD0_SHIFT))&PMU_REG_1P0A_SET_RSVD0_MASK)
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#define PMU_REG_1P0A_SET_BO_MASK 0x10000u
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#define PMU_REG_1P0A_SET_BO_SHIFT 16
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#define PMU_REG_1P0A_SET_OK_MASK 0x20000u
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#define PMU_REG_1P0A_SET_OK_SHIFT 17
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#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_1P0A_SET_REG_TEST_MASK 0xF00000u
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#define PMU_REG_1P0A_SET_REG_TEST_SHIFT 20
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#define PMU_REG_1P0A_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_REG_TEST_SHIFT))&PMU_REG_1P0A_SET_REG_TEST_MASK)
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#define PMU_REG_1P0A_SET_RSVD1_MASK 0xFF000000u
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#define PMU_REG_1P0A_SET_RSVD1_SHIFT 24
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#define PMU_REG_1P0A_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD1_SHIFT))&PMU_REG_1P0A_SET_RSVD1_MASK)
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/* REG_1P0A_CLR Bit Fields */
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#define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_1P0A_CLR_ENABLE_BO_MASK 0x2u
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#define PMU_REG_1P0A_CLR_ENABLE_BO_SHIFT 1
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#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_1P0A_CLR_BO_OFFSET_MASK 0x70u
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#define PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT 4
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#define PMU_REG_1P0A_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0A_CLR_BO_OFFSET_MASK)
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#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_1P0A_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK)
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#define PMU_REG_1P0A_CLR_RSVD0_MASK 0xE000u
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#define PMU_REG_1P0A_CLR_RSVD0_SHIFT 13
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#define PMU_REG_1P0A_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD0_SHIFT))&PMU_REG_1P0A_CLR_RSVD0_MASK)
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#define PMU_REG_1P0A_CLR_BO_MASK 0x10000u
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#define PMU_REG_1P0A_CLR_BO_SHIFT 16
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#define PMU_REG_1P0A_CLR_OK_MASK 0x20000u
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#define PMU_REG_1P0A_CLR_OK_SHIFT 17
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#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_1P0A_CLR_REG_TEST_MASK 0xF00000u
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#define PMU_REG_1P0A_CLR_REG_TEST_SHIFT 20
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#define PMU_REG_1P0A_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_REG_TEST_SHIFT))&PMU_REG_1P0A_CLR_REG_TEST_MASK)
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#define PMU_REG_1P0A_CLR_RSVD1_MASK 0xFF000000u
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#define PMU_REG_1P0A_CLR_RSVD1_SHIFT 24
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#define PMU_REG_1P0A_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD1_SHIFT))&PMU_REG_1P0A_CLR_RSVD1_MASK)
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/* REG_1P0A_TOG Bit Fields */
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#define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_1P0A_TOG_ENABLE_BO_MASK 0x2u
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#define PMU_REG_1P0A_TOG_ENABLE_BO_SHIFT 1
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#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_1P0A_TOG_BO_OFFSET_MASK 0x70u
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#define PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT 4
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#define PMU_REG_1P0A_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0A_TOG_BO_OFFSET_MASK)
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#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_1P0A_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK)
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#define PMU_REG_1P0A_TOG_RSVD0_MASK 0xE000u
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#define PMU_REG_1P0A_TOG_RSVD0_SHIFT 13
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#define PMU_REG_1P0A_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD0_SHIFT))&PMU_REG_1P0A_TOG_RSVD0_MASK)
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#define PMU_REG_1P0A_TOG_BO_MASK 0x10000u
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#define PMU_REG_1P0A_TOG_BO_SHIFT 16
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#define PMU_REG_1P0A_TOG_OK_MASK 0x20000u
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#define PMU_REG_1P0A_TOG_OK_SHIFT 17
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#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_1P0A_TOG_REG_TEST_MASK 0xF00000u
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#define PMU_REG_1P0A_TOG_REG_TEST_SHIFT 20
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#define PMU_REG_1P0A_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_REG_TEST_SHIFT))&PMU_REG_1P0A_TOG_REG_TEST_MASK)
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#define PMU_REG_1P0A_TOG_RSVD1_MASK 0xFF000000u
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#define PMU_REG_1P0A_TOG_RSVD1_SHIFT 24
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#define PMU_REG_1P0A_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD1_SHIFT))&PMU_REG_1P0A_TOG_RSVD1_MASK)
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/* REG_1P0D Bit Fields */
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#define PMU_REG_1P0D_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_1P0D_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_1P0D_ENABLE_BO_MASK 0x2u
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#define PMU_REG_1P0D_ENABLE_BO_SHIFT 1
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#define PMU_REG_1P0D_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_1P0D_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_1P0D_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_1P0D_BO_OFFSET_MASK 0x70u
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#define PMU_REG_1P0D_BO_OFFSET_SHIFT 4
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#define PMU_REG_1P0D_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_BO_OFFSET_SHIFT))&PMU_REG_1P0D_BO_OFFSET_MASK)
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#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_1P0D_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_1P0D_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_1P0D_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_OUTPUT_TRG_MASK)
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#define PMU_REG_1P0D_RSVD0_MASK 0xE000u
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#define PMU_REG_1P0D_RSVD0_SHIFT 13
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#define PMU_REG_1P0D_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD0_SHIFT))&PMU_REG_1P0D_RSVD0_MASK)
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#define PMU_REG_1P0D_BO_MASK 0x10000u
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#define PMU_REG_1P0D_BO_SHIFT 16
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#define PMU_REG_1P0D_OK_MASK 0x20000u
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#define PMU_REG_1P0D_OK_SHIFT 17
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#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_1P0D_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_1P0D_REG_TEST_MASK 0xF00000u
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#define PMU_REG_1P0D_REG_TEST_SHIFT 20
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#define PMU_REG_1P0D_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_REG_TEST_SHIFT))&PMU_REG_1P0D_REG_TEST_MASK)
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#define PMU_REG_1P0D_RSVD1_MASK 0x7F000000u
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#define PMU_REG_1P0D_RSVD1_SHIFT 24
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#define PMU_REG_1P0D_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD1_SHIFT))&PMU_REG_1P0D_RSVD1_MASK)
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#define PMU_REG_1P0D_OVERRIDE_MASK 0x80000000u
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#define PMU_REG_1P0D_OVERRIDE_SHIFT 31
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/* REG_1P0D_SET Bit Fields */
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#define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_1P0D_SET_ENABLE_BO_MASK 0x2u
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#define PMU_REG_1P0D_SET_ENABLE_BO_SHIFT 1
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#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_1P0D_SET_BO_OFFSET_MASK 0x70u
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#define PMU_REG_1P0D_SET_BO_OFFSET_SHIFT 4
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#define PMU_REG_1P0D_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0D_SET_BO_OFFSET_MASK)
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#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_1P0D_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_SET_OUTPUT_TRG_MASK)
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#define PMU_REG_1P0D_SET_RSVD0_MASK 0xE000u
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#define PMU_REG_1P0D_SET_RSVD0_SHIFT 13
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#define PMU_REG_1P0D_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD0_SHIFT))&PMU_REG_1P0D_SET_RSVD0_MASK)
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#define PMU_REG_1P0D_SET_BO_MASK 0x10000u
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#define PMU_REG_1P0D_SET_BO_SHIFT 16
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#define PMU_REG_1P0D_SET_OK_MASK 0x20000u
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#define PMU_REG_1P0D_SET_OK_SHIFT 17
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#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_1P0D_SET_REG_TEST_MASK 0xF00000u
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#define PMU_REG_1P0D_SET_REG_TEST_SHIFT 20
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#define PMU_REG_1P0D_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_REG_TEST_SHIFT))&PMU_REG_1P0D_SET_REG_TEST_MASK)
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#define PMU_REG_1P0D_SET_RSVD1_MASK 0x7F000000u
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#define PMU_REG_1P0D_SET_RSVD1_SHIFT 24
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#define PMU_REG_1P0D_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD1_SHIFT))&PMU_REG_1P0D_SET_RSVD1_MASK)
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#define PMU_REG_1P0D_SET_OVERRIDE_MASK 0x80000000u
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#define PMU_REG_1P0D_SET_OVERRIDE_SHIFT 31
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/* REG_1P0D_CLR Bit Fields */
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#define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_1P0D_CLR_ENABLE_BO_MASK 0x2u
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#define PMU_REG_1P0D_CLR_ENABLE_BO_SHIFT 1
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#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_1P0D_CLR_BO_OFFSET_MASK 0x70u
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#define PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT 4
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#define PMU_REG_1P0D_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0D_CLR_BO_OFFSET_MASK)
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#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_1P0D_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK)
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#define PMU_REG_1P0D_CLR_RSVD0_MASK 0xE000u
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#define PMU_REG_1P0D_CLR_RSVD0_SHIFT 13
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#define PMU_REG_1P0D_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD0_SHIFT))&PMU_REG_1P0D_CLR_RSVD0_MASK)
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#define PMU_REG_1P0D_CLR_BO_MASK 0x10000u
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#define PMU_REG_1P0D_CLR_BO_SHIFT 16
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#define PMU_REG_1P0D_CLR_OK_MASK 0x20000u
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#define PMU_REG_1P0D_CLR_OK_SHIFT 17
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#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_1P0D_CLR_REG_TEST_MASK 0xF00000u
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#define PMU_REG_1P0D_CLR_REG_TEST_SHIFT 20
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#define PMU_REG_1P0D_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_REG_TEST_SHIFT))&PMU_REG_1P0D_CLR_REG_TEST_MASK)
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#define PMU_REG_1P0D_CLR_RSVD1_MASK 0x7F000000u
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#define PMU_REG_1P0D_CLR_RSVD1_SHIFT 24
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#define PMU_REG_1P0D_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD1_SHIFT))&PMU_REG_1P0D_CLR_RSVD1_MASK)
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#define PMU_REG_1P0D_CLR_OVERRIDE_MASK 0x80000000u
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#define PMU_REG_1P0D_CLR_OVERRIDE_SHIFT 31
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/* REG_1P0D_TOG Bit Fields */
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#define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_1P0D_TOG_ENABLE_BO_MASK 0x2u
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#define PMU_REG_1P0D_TOG_ENABLE_BO_SHIFT 1
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#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_1P0D_TOG_BO_OFFSET_MASK 0x70u
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#define PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT 4
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#define PMU_REG_1P0D_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0D_TOG_BO_OFFSET_MASK)
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#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_1P0D_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK)
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#define PMU_REG_1P0D_TOG_RSVD0_MASK 0xE000u
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#define PMU_REG_1P0D_TOG_RSVD0_SHIFT 13
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#define PMU_REG_1P0D_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD0_SHIFT))&PMU_REG_1P0D_TOG_RSVD0_MASK)
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#define PMU_REG_1P0D_TOG_BO_MASK 0x10000u
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#define PMU_REG_1P0D_TOG_BO_SHIFT 16
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#define PMU_REG_1P0D_TOG_OK_MASK 0x20000u
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#define PMU_REG_1P0D_TOG_OK_SHIFT 17
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#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_1P0D_TOG_REG_TEST_MASK 0xF00000u
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#define PMU_REG_1P0D_TOG_REG_TEST_SHIFT 20
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#define PMU_REG_1P0D_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_REG_TEST_SHIFT))&PMU_REG_1P0D_TOG_REG_TEST_MASK)
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#define PMU_REG_1P0D_TOG_RSVD1_MASK 0x7F000000u
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#define PMU_REG_1P0D_TOG_RSVD1_SHIFT 24
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#define PMU_REG_1P0D_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD1_SHIFT))&PMU_REG_1P0D_TOG_RSVD1_MASK)
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#define PMU_REG_1P0D_TOG_OVERRIDE_MASK 0x80000000u
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#define PMU_REG_1P0D_TOG_OVERRIDE_SHIFT 31
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/* REG_HSIC_1P2 Bit Fields */
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#define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_HSIC_1P2_ENABLE_BO_MASK 0x2u
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#define PMU_REG_HSIC_1P2_ENABLE_BO_SHIFT 1
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#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_HSIC_1P2_BO_OFFSET_MASK 0x70u
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#define PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT 4
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#define PMU_REG_HSIC_1P2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_BO_OFFSET_MASK)
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#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_HSIC_1P2_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK)
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#define PMU_REG_HSIC_1P2_RSVD0_MASK 0xE000u
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#define PMU_REG_HSIC_1P2_RSVD0_SHIFT 13
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#define PMU_REG_HSIC_1P2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_RSVD0_MASK)
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#define PMU_REG_HSIC_1P2_BO_MASK 0x10000u
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#define PMU_REG_HSIC_1P2_BO_SHIFT 16
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#define PMU_REG_HSIC_1P2_OK_MASK 0x20000u
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#define PMU_REG_HSIC_1P2_OK_SHIFT 17
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#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_HSIC_1P2_REG_TEST_MASK 0xF00000u
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#define PMU_REG_HSIC_1P2_REG_TEST_SHIFT 20
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#define PMU_REG_HSIC_1P2_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_REG_TEST_MASK)
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#define PMU_REG_HSIC_1P2_RSVD1_MASK 0x7F000000u
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#define PMU_REG_HSIC_1P2_RSVD1_SHIFT 24
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#define PMU_REG_HSIC_1P2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_RSVD1_MASK)
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#define PMU_REG_HSIC_1P2_OVERRIDE_MASK 0x80000000u
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#define PMU_REG_HSIC_1P2_OVERRIDE_SHIFT 31
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/* REG_HSIC_1P2_SET Bit Fields */
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#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK 0x2u
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#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_SHIFT 1
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#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK 0x70u
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#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT 4
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#define PMU_REG_HSIC_1P2_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK)
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#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK)
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#define PMU_REG_HSIC_1P2_SET_RSVD0_MASK 0xE000u
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#define PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT 13
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#define PMU_REG_HSIC_1P2_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD0_MASK)
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#define PMU_REG_HSIC_1P2_SET_BO_MASK 0x10000u
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#define PMU_REG_HSIC_1P2_SET_BO_SHIFT 16
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#define PMU_REG_HSIC_1P2_SET_OK_MASK 0x20000u
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#define PMU_REG_HSIC_1P2_SET_OK_SHIFT 17
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#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK 0xF00000u
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#define PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT 20
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#define PMU_REG_HSIC_1P2_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_SET_REG_TEST_MASK)
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#define PMU_REG_HSIC_1P2_SET_RSVD1_MASK 0x7F000000u
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#define PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT 24
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#define PMU_REG_HSIC_1P2_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD1_MASK)
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#define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK 0x80000000u
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#define PMU_REG_HSIC_1P2_SET_OVERRIDE_SHIFT 31
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/* REG_HSIC_1P2_CLR Bit Fields */
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#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK 0x2u
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#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_SHIFT 1
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#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK 0x70u
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#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT 4
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#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK)
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#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK)
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#define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK 0xE000u
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#define PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT 13
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#define PMU_REG_HSIC_1P2_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD0_MASK)
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#define PMU_REG_HSIC_1P2_CLR_BO_MASK 0x10000u
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#define PMU_REG_HSIC_1P2_CLR_BO_SHIFT 16
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#define PMU_REG_HSIC_1P2_CLR_OK_MASK 0x20000u
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#define PMU_REG_HSIC_1P2_CLR_OK_SHIFT 17
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#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK 0xF00000u
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#define PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT 20
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#define PMU_REG_HSIC_1P2_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK)
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#define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK 0x7F000000u
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#define PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT 24
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#define PMU_REG_HSIC_1P2_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD1_MASK)
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#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK 0x80000000u
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#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_SHIFT 31
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/* REG_HSIC_1P2_TOG Bit Fields */
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#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK 0x2u
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#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_SHIFT 1
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#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK 0x70u
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#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT 4
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#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK)
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#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK)
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#define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK 0xE000u
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#define PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT 13
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#define PMU_REG_HSIC_1P2_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD0_MASK)
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#define PMU_REG_HSIC_1P2_TOG_BO_MASK 0x10000u
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#define PMU_REG_HSIC_1P2_TOG_BO_SHIFT 16
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#define PMU_REG_HSIC_1P2_TOG_OK_MASK 0x20000u
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#define PMU_REG_HSIC_1P2_TOG_OK_SHIFT 17
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#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK 0xF00000u
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#define PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT 20
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#define PMU_REG_HSIC_1P2_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK)
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#define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK 0x7F000000u
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#define PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT 24
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#define PMU_REG_HSIC_1P2_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD1_MASK)
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#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK 0x80000000u
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#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_SHIFT 31
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/* REG_LPSR_1P0 Bit Fields */
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#define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_LPSR_1P0_ENABLE_BO_MASK 0x2u
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#define PMU_REG_LPSR_1P0_ENABLE_BO_SHIFT 1
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#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_LPSR_1P0_BO_OFFSET_MASK 0x70u
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#define PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT 4
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#define PMU_REG_LPSR_1P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_BO_OFFSET_MASK)
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#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_LPSR_1P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK)
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#define PMU_REG_LPSR_1P0_RSVD0_MASK 0xE000u
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#define PMU_REG_LPSR_1P0_RSVD0_SHIFT 13
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#define PMU_REG_LPSR_1P0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_RSVD0_MASK)
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#define PMU_REG_LPSR_1P0_BO_MASK 0x10000u
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#define PMU_REG_LPSR_1P0_BO_SHIFT 16
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#define PMU_REG_LPSR_1P0_OK_MASK 0x20000u
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#define PMU_REG_LPSR_1P0_OK_SHIFT 17
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#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_LPSR_1P0_REG_TEST_MASK 0xF00000u
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#define PMU_REG_LPSR_1P0_REG_TEST_SHIFT 20
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#define PMU_REG_LPSR_1P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_REG_TEST_MASK)
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#define PMU_REG_LPSR_1P0_RSVD1_MASK 0xFF000000u
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#define PMU_REG_LPSR_1P0_RSVD1_SHIFT 24
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#define PMU_REG_LPSR_1P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_RSVD1_MASK)
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/* REG_LPSR_1P0_SET Bit Fields */
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#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK 0x2u
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#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_SHIFT 1
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#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK 0x70u
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#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT 4
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#define PMU_REG_LPSR_1P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK)
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#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK)
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#define PMU_REG_LPSR_1P0_SET_RSVD0_MASK 0xE000u
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#define PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT 13
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#define PMU_REG_LPSR_1P0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD0_MASK)
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#define PMU_REG_LPSR_1P0_SET_BO_MASK 0x10000u
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#define PMU_REG_LPSR_1P0_SET_BO_SHIFT 16
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#define PMU_REG_LPSR_1P0_SET_OK_MASK 0x20000u
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#define PMU_REG_LPSR_1P0_SET_OK_SHIFT 17
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#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK 0xF00000u
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#define PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT 20
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#define PMU_REG_LPSR_1P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_SET_REG_TEST_MASK)
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#define PMU_REG_LPSR_1P0_SET_RSVD1_MASK 0xFF000000u
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#define PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT 24
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#define PMU_REG_LPSR_1P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD1_MASK)
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/* REG_LPSR_1P0_CLR Bit Fields */
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#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK 0x2u
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#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_SHIFT 1
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#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK 0x70u
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#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT 4
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#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK)
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#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK)
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#define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK 0xE000u
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#define PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT 13
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#define PMU_REG_LPSR_1P0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD0_MASK)
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#define PMU_REG_LPSR_1P0_CLR_BO_MASK 0x10000u
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#define PMU_REG_LPSR_1P0_CLR_BO_SHIFT 16
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#define PMU_REG_LPSR_1P0_CLR_OK_MASK 0x20000u
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#define PMU_REG_LPSR_1P0_CLR_OK_SHIFT 17
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#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK 0xF00000u
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#define PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT 20
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#define PMU_REG_LPSR_1P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK)
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#define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK 0xFF000000u
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#define PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT 24
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#define PMU_REG_LPSR_1P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD1_MASK)
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/* REG_LPSR_1P0_TOG Bit Fields */
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#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK 0x2u
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#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_SHIFT 1
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#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u
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#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_SHIFT 3
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#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK 0x70u
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#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT 4
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#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK)
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#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
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#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_SHIFT 7
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#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK)
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#define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK 0xE000u
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#define PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT 13
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#define PMU_REG_LPSR_1P0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD0_MASK)
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#define PMU_REG_LPSR_1P0_TOG_BO_MASK 0x10000u
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#define PMU_REG_LPSR_1P0_TOG_BO_SHIFT 16
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#define PMU_REG_LPSR_1P0_TOG_OK_MASK 0x20000u
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#define PMU_REG_LPSR_1P0_TOG_OK_SHIFT 17
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#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
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#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_SHIFT 18
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#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
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#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_SHIFT 19
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#define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK 0xF00000u
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#define PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT 20
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#define PMU_REG_LPSR_1P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK)
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#define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK 0xFF000000u
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#define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT 24
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#define PMU_REG_LPSR_1P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD1_MASK)
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/* REG_3P0 Bit Fields */
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#define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_3P0_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_3P0_ENABLE_BO_MASK 0x2u
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#define PMU_REG_3P0_ENABLE_BO_SHIFT 1
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#define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_3P0_RSVD0_MASK 0x8u
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#define PMU_REG_3P0_RSVD0_SHIFT 3
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#define PMU_REG_3P0_BO_OFFSET_MASK 0x70u
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#define PMU_REG_3P0_BO_OFFSET_SHIFT 4
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#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK)
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#define PMU_REG_3P0_VBUS_SEL_MASK 0x80u
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#define PMU_REG_3P0_VBUS_SEL_SHIFT 7
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#define PMU_REG_3P0_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_3P0_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK)
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#define PMU_REG_3P0_RSVD1_MASK 0xE000u
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#define PMU_REG_3P0_RSVD1_SHIFT 13
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#define PMU_REG_3P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD1_SHIFT))&PMU_REG_3P0_RSVD1_MASK)
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#define PMU_REG_3P0_BO_VDD3P0_MASK 0x10000u
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#define PMU_REG_3P0_BO_VDD3P0_SHIFT 16
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#define PMU_REG_3P0_OK_VDD3P0_MASK 0x20000u
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#define PMU_REG_3P0_OK_VDD3P0_SHIFT 17
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#define PMU_REG_3P0_REG_TEST_MASK 0x3C0000u
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#define PMU_REG_3P0_REG_TEST_SHIFT 18
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#define PMU_REG_3P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_REG_TEST_SHIFT))&PMU_REG_3P0_REG_TEST_MASK)
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#define PMU_REG_3P0_RSVD2_MASK 0xFFC00000u
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#define PMU_REG_3P0_RSVD2_SHIFT 22
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#define PMU_REG_3P0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD2_SHIFT))&PMU_REG_3P0_RSVD2_MASK)
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/* REG_3P0_SET Bit Fields */
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#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_3P0_SET_ENABLE_BO_MASK 0x2u
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#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT 1
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#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_3P0_SET_RSVD0_MASK 0x8u
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#define PMU_REG_3P0_SET_RSVD0_SHIFT 3
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#define PMU_REG_3P0_SET_BO_OFFSET_MASK 0x70u
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#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT 4
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#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_BO_OFFSET_SHIFT))&PMU_REG_3P0_SET_BO_OFFSET_MASK)
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#define PMU_REG_3P0_SET_VBUS_SEL_MASK 0x80u
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#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT 7
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#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
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#define PMU_REG_3P0_SET_RSVD1_MASK 0xE000u
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#define PMU_REG_3P0_SET_RSVD1_SHIFT 13
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#define PMU_REG_3P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD1_SHIFT))&PMU_REG_3P0_SET_RSVD1_MASK)
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#define PMU_REG_3P0_SET_BO_VDD3P0_MASK 0x10000u
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#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT 16
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#define PMU_REG_3P0_SET_OK_VDD3P0_MASK 0x20000u
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#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT 17
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#define PMU_REG_3P0_SET_REG_TEST_MASK 0x3C0000u
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#define PMU_REG_3P0_SET_REG_TEST_SHIFT 18
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#define PMU_REG_3P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_REG_TEST_SHIFT))&PMU_REG_3P0_SET_REG_TEST_MASK)
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#define PMU_REG_3P0_SET_RSVD2_MASK 0xFFC00000u
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#define PMU_REG_3P0_SET_RSVD2_SHIFT 22
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#define PMU_REG_3P0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD2_SHIFT))&PMU_REG_3P0_SET_RSVD2_MASK)
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/* REG_3P0_CLR Bit Fields */
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#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_3P0_CLR_ENABLE_BO_MASK 0x2u
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#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT 1
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#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_3P0_CLR_RSVD0_MASK 0x8u
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#define PMU_REG_3P0_CLR_RSVD0_SHIFT 3
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#define PMU_REG_3P0_CLR_BO_OFFSET_MASK 0x70u
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#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT 4
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#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_3P0_CLR_BO_OFFSET_MASK)
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#define PMU_REG_3P0_CLR_VBUS_SEL_MASK 0x80u
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#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT 7
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#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
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#define PMU_REG_3P0_CLR_RSVD1_MASK 0xE000u
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#define PMU_REG_3P0_CLR_RSVD1_SHIFT 13
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#define PMU_REG_3P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD1_SHIFT))&PMU_REG_3P0_CLR_RSVD1_MASK)
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#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK 0x10000u
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#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT 16
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#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK 0x20000u
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#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT 17
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#define PMU_REG_3P0_CLR_REG_TEST_MASK 0x3C0000u
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#define PMU_REG_3P0_CLR_REG_TEST_SHIFT 18
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#define PMU_REG_3P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_REG_TEST_SHIFT))&PMU_REG_3P0_CLR_REG_TEST_MASK)
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#define PMU_REG_3P0_CLR_RSVD2_MASK 0xFFC00000u
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#define PMU_REG_3P0_CLR_RSVD2_SHIFT 22
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#define PMU_REG_3P0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD2_SHIFT))&PMU_REG_3P0_CLR_RSVD2_MASK)
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/* REG_3P0_TOG Bit Fields */
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#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK 0x1u
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#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT 0
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#define PMU_REG_3P0_TOG_ENABLE_BO_MASK 0x2u
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#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT 1
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#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK 0x4u
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#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT 2
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#define PMU_REG_3P0_TOG_RSVD0_MASK 0x8u
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#define PMU_REG_3P0_TOG_RSVD0_SHIFT 3
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#define PMU_REG_3P0_TOG_BO_OFFSET_MASK 0x70u
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#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT 4
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#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_3P0_TOG_BO_OFFSET_MASK)
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#define PMU_REG_3P0_TOG_VBUS_SEL_MASK 0x80u
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#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT 7
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#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK 0x1F00u
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#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT 8
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#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
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#define PMU_REG_3P0_TOG_RSVD1_MASK 0xE000u
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#define PMU_REG_3P0_TOG_RSVD1_SHIFT 13
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#define PMU_REG_3P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD1_SHIFT))&PMU_REG_3P0_TOG_RSVD1_MASK)
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#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK 0x10000u
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#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT 16
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#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK 0x20000u
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#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT 17
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#define PMU_REG_3P0_TOG_REG_TEST_MASK 0x3C0000u
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#define PMU_REG_3P0_TOG_REG_TEST_SHIFT 18
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#define PMU_REG_3P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_REG_TEST_SHIFT))&PMU_REG_3P0_TOG_REG_TEST_MASK)
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#define PMU_REG_3P0_TOG_RSVD2_MASK 0xFFC00000u
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#define PMU_REG_3P0_TOG_RSVD2_SHIFT 22
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#define PMU_REG_3P0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD2_SHIFT))&PMU_REG_3P0_TOG_RSVD2_MASK)
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/* REF Bit Fields */
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#define PMU_REF_REFTOP_PWD_MASK 0x1u
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#define PMU_REF_REFTOP_PWD_SHIFT 0
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#define PMU_REF_REFTOP_PWDVBGUP_MASK 0x2u
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#define PMU_REF_REFTOP_PWDVBGUP_SHIFT 1
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#define PMU_REF_REFTOP_LOWPOWER_MASK 0x4u
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#define PMU_REF_REFTOP_LOWPOWER_SHIFT 2
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#define PMU_REF_REFTOP_SELFBIASOFF_MASK 0x8u
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#define PMU_REF_REFTOP_SELFBIASOFF_SHIFT 3
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#define PMU_REF_REFTOP_VBGADJ_MASK 0x70u
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#define PMU_REF_REFTOP_VBGADJ_SHIFT 4
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#define PMU_REF_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_VBGADJ_SHIFT))&PMU_REF_REFTOP_VBGADJ_MASK)
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#define PMU_REF_REFTOP_VBGUP_MASK 0x80u
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#define PMU_REF_REFTOP_VBGUP_SHIFT 7
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#define PMU_REF_REFTOP_BIAS_TST_MASK 0x300u
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#define PMU_REF_REFTOP_BIAS_TST_SHIFT 8
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#define PMU_REF_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_BIAS_TST_SHIFT))&PMU_REF_REFTOP_BIAS_TST_MASK)
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#define PMU_REF_LPBG_SEL_MASK 0x400u
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#define PMU_REF_LPBG_SEL_SHIFT 10
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#define PMU_REF_LPBG_TEST_MASK 0x800u
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#define PMU_REF_LPBG_TEST_SHIFT 11
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#define PMU_REF_REFTOP_IBIAS_OFF_MASK 0x1000u
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#define PMU_REF_REFTOP_IBIAS_OFF_SHIFT 12
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#define PMU_REF_REFTOP_LINREGREF_EN_MASK 0x2000u
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#define PMU_REF_REFTOP_LINREGREF_EN_SHIFT 13
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#define PMU_REF_RSVD1_MASK 0xFFFFC000u
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#define PMU_REF_RSVD1_SHIFT 14
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#define PMU_REF_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_RSVD1_SHIFT))&PMU_REF_RSVD1_MASK)
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/* REF_SET Bit Fields */
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#define PMU_REF_SET_REFTOP_PWD_MASK 0x1u
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#define PMU_REF_SET_REFTOP_PWD_SHIFT 0
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#define PMU_REF_SET_REFTOP_PWDVBGUP_MASK 0x2u
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#define PMU_REF_SET_REFTOP_PWDVBGUP_SHIFT 1
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#define PMU_REF_SET_REFTOP_LOWPOWER_MASK 0x4u
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#define PMU_REF_SET_REFTOP_LOWPOWER_SHIFT 2
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#define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK 0x8u
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#define PMU_REF_SET_REFTOP_SELFBIASOFF_SHIFT 3
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#define PMU_REF_SET_REFTOP_VBGADJ_MASK 0x70u
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#define PMU_REF_SET_REFTOP_VBGADJ_SHIFT 4
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#define PMU_REF_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_VBGADJ_SHIFT))&PMU_REF_SET_REFTOP_VBGADJ_MASK)
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#define PMU_REF_SET_REFTOP_VBGUP_MASK 0x80u
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#define PMU_REF_SET_REFTOP_VBGUP_SHIFT 7
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#define PMU_REF_SET_REFTOP_BIAS_TST_MASK 0x300u
|
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#define PMU_REF_SET_REFTOP_BIAS_TST_SHIFT 8
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#define PMU_REF_SET_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_BIAS_TST_SHIFT))&PMU_REF_SET_REFTOP_BIAS_TST_MASK)
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#define PMU_REF_SET_LPBG_SEL_MASK 0x400u
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#define PMU_REF_SET_LPBG_SEL_SHIFT 10
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#define PMU_REF_SET_LPBG_TEST_MASK 0x800u
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#define PMU_REF_SET_LPBG_TEST_SHIFT 11
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#define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK 0x1000u
|
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#define PMU_REF_SET_REFTOP_IBIAS_OFF_SHIFT 12
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#define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK 0x2000u
|
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#define PMU_REF_SET_REFTOP_LINREGREF_EN_SHIFT 13
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#define PMU_REF_SET_RSVD1_MASK 0xFFFFC000u
|
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#define PMU_REF_SET_RSVD1_SHIFT 14
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#define PMU_REF_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_RSVD1_SHIFT))&PMU_REF_SET_RSVD1_MASK)
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/* REF_CLR Bit Fields */
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#define PMU_REF_CLR_REFTOP_PWD_MASK 0x1u
|
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#define PMU_REF_CLR_REFTOP_PWD_SHIFT 0
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#define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK 0x2u
|
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#define PMU_REF_CLR_REFTOP_PWDVBGUP_SHIFT 1
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#define PMU_REF_CLR_REFTOP_LOWPOWER_MASK 0x4u
|
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#define PMU_REF_CLR_REFTOP_LOWPOWER_SHIFT 2
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#define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK 0x8u
|
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#define PMU_REF_CLR_REFTOP_SELFBIASOFF_SHIFT 3
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#define PMU_REF_CLR_REFTOP_VBGADJ_MASK 0x70u
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#define PMU_REF_CLR_REFTOP_VBGADJ_SHIFT 4
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#define PMU_REF_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_VBGADJ_SHIFT))&PMU_REF_CLR_REFTOP_VBGADJ_MASK)
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#define PMU_REF_CLR_REFTOP_VBGUP_MASK 0x80u
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#define PMU_REF_CLR_REFTOP_VBGUP_SHIFT 7
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#define PMU_REF_CLR_REFTOP_BIAS_TST_MASK 0x300u
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#define PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT 8
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#define PMU_REF_CLR_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT))&PMU_REF_CLR_REFTOP_BIAS_TST_MASK)
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#define PMU_REF_CLR_LPBG_SEL_MASK 0x400u
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#define PMU_REF_CLR_LPBG_SEL_SHIFT 10
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#define PMU_REF_CLR_LPBG_TEST_MASK 0x800u
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#define PMU_REF_CLR_LPBG_TEST_SHIFT 11
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#define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK 0x1000u
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#define PMU_REF_CLR_REFTOP_IBIAS_OFF_SHIFT 12
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#define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK 0x2000u
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#define PMU_REF_CLR_REFTOP_LINREGREF_EN_SHIFT 13
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#define PMU_REF_CLR_RSVD1_MASK 0xFFFFC000u
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#define PMU_REF_CLR_RSVD1_SHIFT 14
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#define PMU_REF_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_RSVD1_SHIFT))&PMU_REF_CLR_RSVD1_MASK)
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/* REF_TOG Bit Fields */
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#define PMU_REF_TOG_REFTOP_PWD_MASK 0x1u
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#define PMU_REF_TOG_REFTOP_PWD_SHIFT 0
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#define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK 0x2u
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#define PMU_REF_TOG_REFTOP_PWDVBGUP_SHIFT 1
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#define PMU_REF_TOG_REFTOP_LOWPOWER_MASK 0x4u
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#define PMU_REF_TOG_REFTOP_LOWPOWER_SHIFT 2
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#define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK 0x8u
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#define PMU_REF_TOG_REFTOP_SELFBIASOFF_SHIFT 3
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#define PMU_REF_TOG_REFTOP_VBGADJ_MASK 0x70u
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#define PMU_REF_TOG_REFTOP_VBGADJ_SHIFT 4
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#define PMU_REF_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_VBGADJ_SHIFT))&PMU_REF_TOG_REFTOP_VBGADJ_MASK)
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#define PMU_REF_TOG_REFTOP_VBGUP_MASK 0x80u
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#define PMU_REF_TOG_REFTOP_VBGUP_SHIFT 7
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#define PMU_REF_TOG_REFTOP_BIAS_TST_MASK 0x300u
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#define PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT 8
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#define PMU_REF_TOG_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT))&PMU_REF_TOG_REFTOP_BIAS_TST_MASK)
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#define PMU_REF_TOG_LPBG_SEL_MASK 0x400u
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#define PMU_REF_TOG_LPBG_SEL_SHIFT 10
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#define PMU_REF_TOG_LPBG_TEST_MASK 0x800u
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#define PMU_REF_TOG_LPBG_TEST_SHIFT 11
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#define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK 0x1000u
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#define PMU_REF_TOG_REFTOP_IBIAS_OFF_SHIFT 12
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#define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK 0x2000u
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#define PMU_REF_TOG_REFTOP_LINREGREF_EN_SHIFT 13
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#define PMU_REF_TOG_RSVD1_MASK 0xFFFFC000u
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#define PMU_REF_TOG_RSVD1_SHIFT 14
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#define PMU_REF_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_RSVD1_SHIFT))&PMU_REF_TOG_RSVD1_MASK)
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/* LOWPWR_CTRL Bit Fields */
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#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK 0x3u
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#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT 0
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#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK)
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#define PMU_LOWPWR_CTRL_RSVD0_MASK 0xFCu
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#define PMU_LOWPWR_CTRL_RSVD0_SHIFT 2
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#define PMU_LOWPWR_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_RSVD0_MASK)
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#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK 0x100u
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#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT 8
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#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK 0x200u
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#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT 9
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#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK 0x400u
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#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT 10
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#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK 0x800u
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#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT 11
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#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK 0x1000u
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#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT 12
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#define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK 0x2000u
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#define PMU_LOWPWR_CTRL_GPU_PWRGATE_SHIFT 13
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#define PMU_LOWPWR_CTRL_CONTROL0_MASK 0xFFC000u
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#define PMU_LOWPWR_CTRL_CONTROL0_SHIFT 14
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#define PMU_LOWPWR_CTRL_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CONTROL0_MASK)
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#define PMU_LOWPWR_CTRL_CONTROL1_MASK 0xFF000000u
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#define PMU_LOWPWR_CTRL_CONTROL1_SHIFT 24
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#define PMU_LOWPWR_CTRL_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CONTROL1_MASK)
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/* LOWPWR_CTRL_SET Bit Fields */
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#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u
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#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0
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#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK)
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#define PMU_LOWPWR_CTRL_SET_RSVD0_MASK 0xFCu
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#define PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT 2
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#define PMU_LOWPWR_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_SET_RSVD0_MASK)
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#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u
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#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8
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#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u
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#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9
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#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u
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#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10
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#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u
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#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11
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#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x1000u
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#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 12
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#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x2000u
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#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 13
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#define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK 0xFFC000u
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#define PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT 14
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#define PMU_LOWPWR_CTRL_SET_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL0_MASK)
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#define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK 0xFF000000u
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#define PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT 24
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#define PMU_LOWPWR_CTRL_SET_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL1_MASK)
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/* LOWPWR_CTRL_CLR Bit Fields */
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#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u
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#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0
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#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK)
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#define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK 0xFCu
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#define PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT 2
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#define PMU_LOWPWR_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_CLR_RSVD0_MASK)
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#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u
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#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8
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#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u
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#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9
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#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u
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#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10
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#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u
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#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11
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#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x1000u
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#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 12
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#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x2000u
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#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 13
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#define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK 0xFFC000u
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#define PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT 14
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#define PMU_LOWPWR_CTRL_CLR_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK)
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#define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK 0xFF000000u
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#define PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT 24
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#define PMU_LOWPWR_CTRL_CLR_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK)
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/* LOWPWR_CTRL_TOG Bit Fields */
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#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u
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#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0
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#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK)
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#define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK 0xFCu
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#define PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT 2
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#define PMU_LOWPWR_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_TOG_RSVD0_MASK)
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#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u
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#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8
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#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u
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#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9
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#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u
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#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10
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#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u
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#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11
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#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x1000u
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#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 12
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#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x2000u
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#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 13
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#define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK 0xFFC000u
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#define PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT 14
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#define PMU_LOWPWR_CTRL_TOG_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK)
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#define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK 0xFF000000u
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#define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24
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#define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK)
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/* HW_ANADIG_TEMPSENSE0 Bit Fields */
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT 9
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT 18
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK 0xF8000000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT 27
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK)
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/* HW_ANADIG_TEMPSENSE0_SET Bit Fields */
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT 9
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT 18
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT 27
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK)
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/* HW_ANADIG_TEMPSENSE0_CLR Bit Fields */
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT 9
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT 18
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT 27
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK)
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/* HW_ANADIG_TEMPSENSE0_TOG Bit Fields */
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT 9
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT 18
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT 27
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#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK)
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/* HW_ANADIG_TEMPSENSE1 Bit Fields */
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_SHIFT 9
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_SHIFT 10
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_SHIFT 11
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK 0xF000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT 12
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT 16
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK)
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/* HW_ANADIG_TEMPSENSE1_SET Bit Fields */
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_SHIFT 9
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_SHIFT 10
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_SHIFT 11
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT 12
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 16
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
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/* HW_ANADIG_TEMPSENSE1_CLR Bit Fields */
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_SHIFT 9
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_SHIFT 10
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_SHIFT 11
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 16
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
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/* HW_ANADIG_TEMPSENSE1_TOG Bit Fields */
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_SHIFT 9
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_SHIFT 10
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_SHIFT 11
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT 12
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 16
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#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
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/* HW_ANADIG_TEMPSENSE_TRIM Bit Fields */
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT 5
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_SHIFT 7
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT 8
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT 17
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT 20
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT 24
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT 29
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK)
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/* HW_ANADIG_TEMPSENSE_TRIM_SET Bit Fields */
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT 5
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_SHIFT 7
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT 8
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT 17
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT 20
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT 24
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT 29
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK)
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/* HW_ANADIG_TEMPSENSE_TRIM_CLR Bit Fields */
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT 5
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_SHIFT 7
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT 8
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT 17
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT 20
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT 24
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT 29
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK)
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/* HW_ANADIG_TEMPSENSE_TRIM_TOG Bit Fields */
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT 5
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_SHIFT 7
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT 8
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT 17
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT 20
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT 24
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK)
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29
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#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK)
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#define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i))
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#define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i))
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#define CCM_SCTRL(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i))
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#define CCM_CCGR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i))
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#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i))
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#define CCM_GPR_SET(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 4)
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#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4)
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#define CCM_SCTRL_SET(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4)
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#define CCM_CCGR_SET(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 4)
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#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4)
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#define CCM_GPR_CLR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 8)
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#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8)
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#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8)
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#define CCM_CCGR_CLR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 8)
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#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8)
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#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 12)
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#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12)
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#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12)
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#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 12)
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#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
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#define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i))
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#define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i))
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#define HW_CCM_SCTRL_WR(i, v) writel((v), CCM_SCTRL(i))
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#define HW_CCM_CCGR_WR(i, v) writel((v), CCM_CCGR(i))
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#define HW_CCM_ROOT_TARGET_WR(i, v) writel((v), CCM_ROOT_TARGET(i))
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#define HW_CCM_GPR_RD(i) readl(CCM_GPR(i))
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#define HW_CCM_CCM_OBSERVE_RD(i) readl(CCM_OBSERVE(i))
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#define HW_CCM_SCTRL_RD(i) readl(CCM_SCTRL(i))
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#define HW_CCM_CCGR_RD(i) readl(CCM_CCGR(i))
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#define HW_CCM_ROOT_TARGET_RD(i) readl(CCM_ROOT_TARGET(i))
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#define HW_CCM_GPR_SET(i, v) writel((v), CCM_GPR_SET(i))
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#define HW_CCM_CCM_OBSERVE_SET(i, v) writel((v), CCM_CCM_OBSERVE_SET(i))
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#define HW_CCM_SCTRL_SET(i, v) writel((v), CCM_SCTRL_SET(i))
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#define HW_CCM_CCGR_SET(i, v) writel((v), CCM_CCGR_SET(i))
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#define HW_CCM_ROOT_TARGET_SET(i, v) writel((v), CCM_ROOT_TARGET_SET(i))
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#define HW_CCM_GPR_CLR(i, v) writel((v), CCM_GPR_CLR(i))
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#define HW_CCM_CCM_OBSERVE_CLR(i, v) writel((v), CCM_CCM_OBSERVE_CLR(i))
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#define HW_CCM_SCTRL_CLR(i, v) writel((v), CCM_SCTRL_CLR(i))
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#define HW_CCM_CCGR_CLR(i, v) writel((v), CCM_CCGR_CLR(i))
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#define HW_CCM_ROOT_TARGET_CLR(i, v) writel((v), CCM_ROOT_TARGET_CLR(i))
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#define HW_CCM_GPR_TOGGLE(i, v) writel((v), CCM_GPR_TOGGLE(i))
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#define HW_CCM_CCM_OBSERVE_TOGGLE(i, v) writel((v), CCM_CCM_OBSERVE_TOGGLE(i))
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#define HW_CCM_SCTRL_TOGGLE(i, v) writel((v), CCM_SCTRL_TOGGLE(i))
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#define HW_CCM_CCGR_TOGGLE(i, v) writel((v), CCM_CCGR_TOGGLE(i))
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#define HW_CCM_ROOT_TARGET_TOGGLE(i, v) writel((v), CCM_ROOT_TARGET_TOGGLE(i))
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#define CCM_CLK_ON_MSK 0x03
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#define CCM_CLK_ON_N_N 0x00 /* Domain clocks not needed */
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#define CCM_CLK_ON_R_W 0x02 /* Domain clocks needed when in RUN and WAIT */
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/* CCGR Mapping */
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#define CCGR_IDX_DDR 19 /* CCM_CCGR19 */
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#define CCM_ROOT_TGT_POST_DIV_SHIFT 0
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#define CCM_ROOT_TGT_PRE_DIV_SHIFT 15
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#define CCM_ROOT_TGT_MUX_SHIFT 24
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#define CCM_ROOT_TGT_ENABLE_SHIFT 28
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#define CCM_ROOT_TGT_POST_DIV_MSK 0x3F
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#define CCM_ROOT_TGT_PRE_DIV_MSK (0x07 << CCM_ROOT_TGT_PRE_DIV_SHIFT)
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#define CCM_ROOT_TGT_MUX_MSK (0x07 << CCM_ROOT_TGT_MUX_SHIFT)
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#define CCM_ROOT_TGT_ENABLE_MSK (0x01 << CCM_ROOT_TGT_ENABLE_SHIFT)
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#define CCM_ROOT_TGT_POST_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_POST_DIV_SHIFT) & CCM_ROOT_TGT_POST_DIV_MSK)
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#define CCM_ROOT_TGT_PRE_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_PRE_DIV_SHIFT) & CCM_ROOT_TGT_PRE_DIV_MSK)
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#define CCM_ROOT_TGT_MUX_TO(x) ((((x) - 1) << CCM_ROOT_TGT_MUX_SHIFT) & CCM_ROOT_TGT_MUX_MSK)
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/*
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* Field values definition for clock slice TARGET register
|
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*/
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#define CLK_ROOT_ON 0x10000000
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#define CLK_ROOT_OFF 0x0
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#define CLK_ROOT_ENABLE_MASK 0x10000000
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#define CLK_ROOT_ENABLE_SHIFT 28
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#define CLK_ROOT_ALT0 0x00000000
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#define CLK_ROOT_ALT1 0x01000000
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#define CLK_ROOT_ALT2 0x02000000
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#define CLK_ROOT_ALT3 0x03000000
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#define CLK_ROOT_ALT4 0x04000000
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#define CLK_ROOT_ALT5 0x05000000
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#define CLK_ROOT_ALT6 0x06000000
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#define CLK_ROOT_ALT7 0x07000000
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#define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007
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#define CLK_ROOT_POST_DIV_MASK 0x0000003f
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#define CLK_ROOT_POST_DIV_SHIFT 0
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#define CLK_ROOT_POST_DIV(n) ((n << CLK_ROOT_POST_DIV_SHIFT) & CLK_ROOT_POST_DIV_MASK)
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#define CLK_ROOT_AUTO_DIV_MASK 0x00000700
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#define CLK_ROOT_AUTO_DIV_SHIFT 8
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#define CLK_ROOT_AUTO_DIV(n) ((n << CLK_ROOT_AUTO_DIV_SHIFT) & CLK_ROOT_AUTO_DIV_MASK)
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#define CLK_ROOT_AUTO_EN_MASK 0x00001000
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#define CLK_ROOT_AUTO_EN 0x00001000
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#define CLK_ROOT_PRE_DIV_MASK 0x00070000
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#define CLK_ROOT_PRE_DIV_SHIFT 16
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#define CLK_ROOT_PRE_DIV(n) ((n << CLK_ROOT_PRE_DIV_SHIFT) & CLK_ROOT_PRE_DIV_MASK)
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#define CLK_ROOT_MUX_MASK 0x07000000
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#define CLK_ROOT_MUX_SHIFT 24
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#define CLK_ROOT_EN_MASK 0x10000000
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#define CLK_ROOT_AUTO_ON 0x00001000
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#define CLK_ROOT_AUTO_OFF 0x0
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/* ARM_A7_CLK_ROOT */
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#define ARM_A7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define ARM_A7_CLK_ROOT_FROM_PLL_ARM_MAIN_800M_CLK 0x01000000
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#define ARM_A7_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x03000000
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#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
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#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000
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#define ARM_A7_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000
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#define ARM_A7_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
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#define ARM_A7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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/* ARM_M4_CLK_ROOT */
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#define ARM_M4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define ARM_M4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000
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#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
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#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000
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#define ARM_M4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x02000000
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#define ARM_M4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
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#define ARM_M4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
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#define ARM_M4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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/* ARM_M0_CLK_ROOT */
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#define ARM_M0_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define ARM_M0_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000
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#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
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#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x03000000
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#define ARM_M0_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x02000000
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#define ARM_M0_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
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#define ARM_M0_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
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#define ARM_M0_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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/* MAIN_AXI_CLK_ROOT */
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#define MAIN_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define MAIN_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
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#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000
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#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000
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#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
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#define MAIN_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000
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#define MAIN_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
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#define MAIN_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
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/* DISP_AXI_CLK_ROOT */
|
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#define DISP_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define DISP_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
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#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000
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#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x04000000
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#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000
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#define DISP_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000
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#define DISP_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
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#define DISP_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
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|
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/* ENET_AXI_CLK_ROOT */
|
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#define ENET_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
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#define ENET_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
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#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000
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#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000
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#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
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#define ENET_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000
|
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#define ENET_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
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#define ENET_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
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|
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/* NAND_USDHC_BUS_CLK_ROOT */
|
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#define NAND_USDHC_BUS_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
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#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
|
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#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x03000000
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#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000
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#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x04000000
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#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000
|
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#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
|
|
#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000
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|
|
/* AHB_CLK_ROOT */
|
|
#define AHB_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
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#define AHB_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
|
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#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000
|
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#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
|
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#define AHB_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
|
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#define AHB_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
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#define AHB_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
|
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#define AHB_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
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|
|
/* DRAM_PHYM_CLK_ROOT */
|
|
#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000
|
|
#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_PHYM_ALT_CLK_ROOT 0x01000000
|
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|
|
/* DRAM_CLK_ROOT */
|
|
#define DRAM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000
|
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#define DRAM_CLK_ROOT_FROM_PLL_DRAM_ALT_CLK_ROOT 0x01000000
|
|
|
|
/* DRAM_PHYM_ALT_CLK_ROOT */
|
|
#define DRAM_PHYM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000
|
|
#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000
|
|
#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000
|
|
#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
|
|
#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
|
|
#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
|
|
#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000
|
|
|
|
/* DRAM_ALT_CLK_ROOT */
|
|
#define DRAM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define DRAM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000
|
|
#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000
|
|
#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000
|
|
#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x07000000
|
|
#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
|
|
#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x04000000
|
|
#define DRAM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
|
|
|
|
/* USB_HSIC_CLK_ROOT */
|
|
#define USB_HSIC_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000
|
|
#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x03000000
|
|
#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
|
|
#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x05000000
|
|
#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
|
|
#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
|
|
#define USB_HSIC_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x02000000
|
|
|
|
/* PCIE_CTRL_CLK_ROOT */
|
|
#define PCIE_CTRL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define PCIE_CTRL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000
|
|
#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000
|
|
#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x06000000
|
|
#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000
|
|
#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x07000000
|
|
#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000
|
|
#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x01000000
|
|
|
|
/* PCIE_PHY_CLK_ROOT */
|
|
#define PCIE_PHY_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define PCIE_PHY_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x07000000
|
|
#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000
|
|
#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
|
|
#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_1 0x03000000
|
|
#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_2 0x04000000
|
|
#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
|
|
#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
|
|
|
|
/* EPDC_PIXEL_CLK_ROOT */
|
|
#define EPDC_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
|
|
#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
|
|
#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000
|
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#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000
|
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#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000
|
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#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x06000000
|
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#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
|
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|
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/* LCDIF_PIXEL_CLK_ROOT */
|
|
#define LCDIF_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
|
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#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
|
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#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
|
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#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000
|
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#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
|
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#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
|
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#define LCDIF_PIXEL_CLK_ROOT_FROM_EXT_CLK_3 0x03000000
|
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|
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/* MIPI_DSI_EXTSER_CLK_ROOT */
|
|
#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000
|
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#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
|
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#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000
|
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#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000
|
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#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000
|
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#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000
|
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#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
|
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|
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/* MIPI_CSI_WARP_CLK_ROOT */
|
|
#define MIPI_CSI_WARP_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000
|
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#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
|
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#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000
|
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#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000
|
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#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000
|
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#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000
|
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#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
|
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|
|
/* MIPI_DPHY_REF_CLK_ROOT */
|
|
#define MIPI_DPHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
|
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#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
|
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#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x03000000
|
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#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
|
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#define MIPI_DPHY_REF_CLK_ROOT_FROM_REF_1M_CLK 0x04000000
|
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#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
|
|
#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
|
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|
|
/* SAI1_CLK_ROOT */
|
|
#define SAI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
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#define SAI1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
|
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#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
|
|
#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
|
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#define SAI1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
|
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#define SAI1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
|
|
#define SAI1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
|
|
#define SAI1_CLK_ROOT_FROM_EXT_CLK_2 0x07000000
|
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|
|
/* SAI2_CLK_ROOT */
|
|
#define SAI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define SAI2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
|
|
#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
|
|
#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
|
|
#define SAI2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
|
|
#define SAI2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
|
|
#define SAI2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
|
|
#define SAI2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000
|
|
|
|
/* SAI3_CLK_ROOT */
|
|
#define SAI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define SAI3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
|
|
#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
|
|
#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
|
|
#define SAI3_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
|
|
#define SAI3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
|
|
#define SAI3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
|
|
#define SAI3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
|
|
|
|
/* SPDIF_CLK_ROOT */
|
|
#define SPDIF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define SPDIF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
|
|
#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
|
|
#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
|
|
#define SPDIF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
|
|
#define SPDIF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
|
|
#define SPDIF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
|
|
#define SPDIF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
|
|
|
|
/* ENET1_REF_CLK_ROOT */
|
|
#define ENET1_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define ENET1_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000
|
|
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
|
|
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
|
|
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
|
|
#define ENET1_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
|
|
#define ENET1_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
|
|
#define ENET1_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000
|
|
|
|
/* ENET1_TIME_CLK_ROOT */
|
|
#define ENET1_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
|
|
#define ENET1_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
|
|
#define ENET1_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
|
|
#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000
|
|
#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000
|
|
#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
|
|
#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
|
|
|
|
/* ENET2_REF_CLK_ROOT */
|
|
#define ENET2_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define ENET2_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000
|
|
#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
|
|
#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
|
|
#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
|
|
#define ENET2_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
|
|
#define ENET2_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
|
|
#define ENET2_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000
|
|
|
|
/* ENET2_TIME_CLK_ROOT */
|
|
#define ENET2_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
|
|
#define ENET2_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
|
|
#define ENET2_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
|
|
#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000
|
|
#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000
|
|
#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
|
|
#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
|
|
|
|
/* ENET_PHY_REF_CLK_ROOT */
|
|
#define ENET_PHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000
|
|
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x07000000
|
|
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x03000000
|
|
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
|
|
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
|
|
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
|
|
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
|
|
|
|
/* EIM_CLK_ROOT */
|
|
#define EIM_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define EIM_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
|
|
#define EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
|
|
#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x04000000
|
|
#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
|
|
#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x05000000
|
|
#define EIM_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
|
|
#define EIM_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
|
|
|
|
/* NAND_CLK_ROOT */
|
|
#define NAND_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define NAND_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
|
|
#define NAND_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000
|
|
#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000
|
|
#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000
|
|
#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000
|
|
#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
|
|
#define NAND_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
|
|
|
|
/* QSPI_CLK_ROOT */
|
|
#define QSPI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define QSPI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
|
|
#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
|
|
#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000
|
|
#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000
|
|
#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
|
|
#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
|
|
#define QSPI_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
|
|
|
|
/* USDHC1_CLK_ROOT */
|
|
#define USDHC1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define USDHC1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
|
|
#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000
|
|
#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
|
|
#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
|
|
#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
|
|
#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
|
|
#define USDHC1_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
|
|
|
|
/* USDHC2_CLK_ROOT */
|
|
#define USDHC2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define USDHC2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
|
|
#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000
|
|
#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
|
|
#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
|
|
#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
|
|
#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
|
|
#define USDHC2_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
|
|
|
|
/* USDHC3_CLK_ROOT */
|
|
#define USDHC3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define USDHC3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
|
|
#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000
|
|
#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
|
|
#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
|
|
#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
|
|
#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
|
|
#define USDHC3_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
|
|
|
|
/* CAN1_CLK_ROOT */
|
|
#define CAN1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define CAN1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
|
|
#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
|
|
#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
|
|
#define CAN1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000
|
|
#define CAN1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
|
|
#define CAN1_CLK_ROOT_FROM_EXT_CLK_1 0x06000000
|
|
#define CAN1_CLK_ROOT_FROM_EXT_CLK_4 0x07000000
|
|
|
|
/* CAN2_CLK_ROOT */
|
|
#define CAN2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define CAN2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
|
|
#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
|
|
#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
|
|
#define CAN2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000
|
|
#define CAN2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
|
|
#define CAN2_CLK_ROOT_FROM_EXT_CLK_1 0x06000000
|
|
#define CAN2_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
|
|
|
|
/* I2C1_CLK_ROOT */
|
|
#define I2C1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define I2C1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
|
|
#define I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
|
|
#define I2C1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000
|
|
#define I2C1_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
|
|
#define I2C1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
|
|
#define I2C1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
|
|
#define I2C1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000
|
|
|
|
/* I2C2_CLK_ROOT */
|
|
#define I2C2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define I2C2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
|
|
#define I2C2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
|
|
#define I2C2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000
|
|
#define I2C2_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
|
|
#define I2C2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
|
|
#define I2C2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
|
|
#define I2C2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000
|
|
|
|
/* I2C3_CLK_ROOT */
|
|
#define I2C3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define I2C3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
|
|
#define I2C3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
|
|
#define I2C3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000
|
|
#define I2C3_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
|
|
#define I2C3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
|
|
#define I2C3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
|
|
#define I2C3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000
|
|
|
|
/* I2C4_CLK_ROOT */
|
|
#define I2C4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define I2C4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
|
|
#define I2C4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
|
|
#define I2C4_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000
|
|
#define I2C4_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
|
|
#define I2C4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
|
|
#define I2C4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
|
|
#define I2C4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000
|
|
|
|
/* UART1_CLK_ROOT */
|
|
#define UART1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
|
|
#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
|
|
#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
|
|
#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
|
|
#define UART1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
|
|
#define UART1_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
|
|
#define UART1_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
|
|
|
|
/* UART2_CLK_ROOT */
|
|
#define UART2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
|
|
#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
|
|
#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
|
|
#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
|
|
#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
|
|
#define UART2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
|
|
#define UART2_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
|
|
#define UART2_CLK_ROOT_FROM_EXT_CLK_3 0x06000000
|
|
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/* UART3_CLK_ROOT */
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#define UART3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
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#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
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#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
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#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
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#define UART3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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#define UART3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
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#define UART3_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
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/* UART4_CLK_ROOT */
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#define UART4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
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#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
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#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
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#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
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#define UART4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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#define UART4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
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#define UART4_CLK_ROOT_FROM_EXT_CLK_3 0x06000000
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/* UART5_CLK_ROOT */
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#define UART5_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
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#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
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#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
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#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
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#define UART5_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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#define UART5_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
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#define UART5_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
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/* UART6_CLK_ROOT */
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#define UART6_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
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#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
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#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
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#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
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#define UART6_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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#define UART6_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
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#define UART6_CLK_ROOT_FROM_EXT_CLK_3 0x06000000
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/* UART7_CLK_ROOT */
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#define UART7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
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#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
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#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
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#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
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#define UART7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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#define UART7_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
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#define UART7_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
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/* ECSPI1_CLK_ROOT */
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#define ECSPI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
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#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
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#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000
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#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
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#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
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#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
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#define ECSPI1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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/* ECSPI2_CLK_ROOT */
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#define ECSPI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
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#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
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#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000
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#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
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#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
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#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
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#define ECSPI2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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/* ECSPI3_CLK_ROOT */
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#define ECSPI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
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#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
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#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000
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#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
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#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
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#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
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#define ECSPI3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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/* ECSPI4_CLK_ROOT */
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#define ECSPI4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
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#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
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#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000
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#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
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#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
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#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
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#define ECSPI4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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/* PWM1_CLK_ROOT */
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#define PWM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define PWM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
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#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
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#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
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#define PWM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
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#define PWM1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
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#define PWM1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
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#define PWM1_CLK_ROOT_FROM_EXT_CLK_1 0x05000000
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/* PWM2_CLK_ROOT */
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#define PWM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define PWM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
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#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
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#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
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#define PWM2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
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#define PWM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
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#define PWM2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
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#define PWM2_CLK_ROOT_FROM_EXT_CLK_1 0x05000000
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/* PWM3_CLK_ROOT */
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#define PWM3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define PWM3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
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#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
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#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
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#define PWM3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
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#define PWM3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
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#define PWM3_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
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#define PWM3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
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/* PWM4_CLK_ROOT */
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#define PWM4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define PWM4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
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#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
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#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
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#define PWM4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
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#define PWM4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
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#define PWM4_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
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#define PWM4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
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/* FLEXTIMER1_CLK_ROOT */
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#define FLEXTIMER1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define FLEXTIMER1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
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#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
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#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
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#define FLEXTIMER1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
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#define FLEXTIMER1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
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#define FLEXTIMER1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
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#define FLEXTIMER1_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
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/* FLEXTIMER2_CLK_ROOT */
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#define FLEXTIMER2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define FLEXTIMER2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
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#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
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#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
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#define FLEXTIMER2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
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#define FLEXTIMER2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
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#define FLEXTIMER2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
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#define FLEXTIMER2_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
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/* SIM1_CLK_ROOT */
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#define SIM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define SIM1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
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#define SIM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
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#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
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#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
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#define SIM1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
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#define SIM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
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#define SIM1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000
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/* SIM2_CLK_ROOT */
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#define SIM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define SIM2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
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#define SIM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
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#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
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#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
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#define SIM2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
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#define SIM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
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#define SIM2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000
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/* GPT1_CLK_ROOT */
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#define GPT1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define GPT1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
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#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
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#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
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#define GPT1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
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#define GPT1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
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#define GPT1_CLK_ROOT_FROM_REF_1M_CLK 0x05000000
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#define GPT1_CLK_ROOT_FROM_EXT_CLK_1 0x07000000
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/* GPT2_CLK_ROOT */
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#define GPT2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define GPT2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
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#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
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#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
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#define GPT2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
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#define GPT2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
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#define GPT2_CLK_ROOT_FROM_REF_1M_CLK 0x05000000
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#define GPT2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000
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/* GPT3_CLK_ROOT */
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#define GPT3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define GPT3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
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#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
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#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
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#define GPT3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
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#define GPT3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
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#define GPT3_CLK_ROOT_FROM_REF_1M_CLK 0x05000000
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#define GPT3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
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/* GPT4_CLK_ROOT */
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#define GPT4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define GPT4_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
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#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
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#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
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#define GPT4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
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#define GPT4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
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#define GPT4_CLK_ROOT_FROM_REF_1M_CLK 0x05000000
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#define GPT4_CLK_ROOT_FROM_EXT_CLK_4 0x07000000
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/* TRACE_CLK_ROOT */
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#define TRACE_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define TRACE_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
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#define TRACE_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
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#define TRACE_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
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#define TRACE_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
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#define TRACE_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
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#define TRACE_CLK_ROOT_FROM_EXT_CLK_1 0x06000000
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#define TRACE_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
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/* WDOG_CLK_ROOT */
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#define WDOG_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define WDOG_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
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#define WDOG_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
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#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD1_166M_CLK 0x07000000
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#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
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#define WDOG_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
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#define WDOG_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
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#define WDOG_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
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/* CSI_MCLK_CLK_ROOT */
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#define CSI_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define CSI_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
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#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
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#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
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#define CSI_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
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#define CSI_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
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#define CSI_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
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#define CSI_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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/* AUDIO_MCLK_CLK_ROOT */
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#define AUDIO_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
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#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
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#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
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#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
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#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
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#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
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#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
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/* WRCLK_CLK_ROOT */
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#define WRCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
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#define WRCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
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#define WRCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000
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#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
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#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
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#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x06000000
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#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x01000000
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#define WRCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x03000000
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/* IPP_DO_CLKO1 */
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#define IPP_DO_CLKO1_FROM_OSC_24M_CLK 0x00000000
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#define IPP_DO_CLKO1_FROM_PLL_DRAM_MAIN_533M_CLK 0x06000000
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#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000
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#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000
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#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD0_196M_CLK 0x03000000
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#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD3_CLK 0x04000000
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#define IPP_DO_CLKO1_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000
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#define IPP_DO_CLKO1_FROM_REF_1M_CLK 0x07000000
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/* IPP_DO_CLKO2 */
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#define IPP_DO_CLKO2_FROM_OSC_24M_CLK 0x00000000
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#define IPP_DO_CLKO2_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
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#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
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#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD1_166M_CLK 0x03000000
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#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD4_CLK 0x04000000
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#define IPP_DO_CLKO2_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
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#define IPP_DO_CLKO2_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
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#define IPP_DO_CLKO2_FROM_OSC_32K_CLK 0x07000000
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#endif
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