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bf438dbc6d
Upstream linux commit fb3bff5b407e58. This patch enables support to read the ECC strength and size from the NAND flash using Toshiba Memory SLC NAND extended-ID. This patch is based on the information of the 6th ID byte of the Toshiba Memory SLC NAND. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
79 lines
2.2 KiB
C
79 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Free Electrons
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* Copyright (C) 2017 NextThing Co
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*
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* Author: Boris Brezillon <boris.brezillon@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bug.h>
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#include <linux/mtd/rawnand.h>
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static void toshiba_nand_decode_id(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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nand_decode_ext_id(chip);
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/*
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* Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
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* 512B page. For Toshiba SLC, we decode the 5th/6th byte as
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* follows:
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* - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
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* 110b -> 24nm
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* - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
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*/
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if (chip->id.len >= 6 && nand_is_slc(chip) &&
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(chip->id.data[5] & 0x7) == 0x6 /* 24nm */ &&
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!(chip->id.data[4] & 0x80) /* !BENAND */)
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mtd->oobsize = 32 * mtd->writesize >> 9;
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/*
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* Extract ECC requirements from 6th id byte.
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* For Toshiba SLC, ecc requrements are as follows:
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* - 43nm: 1 bit ECC for each 512Byte is required.
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* - 32nm: 4 bit ECC for each 512Byte is required.
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* - 24nm: 8 bit ECC for each 512Byte is required.
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*/
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if (chip->id.len >= 6 && nand_is_slc(chip)) {
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chip->ecc_step_ds = 512;
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switch (chip->id.data[5] & 0x7) {
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case 0x4:
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chip->ecc_strength_ds = 1;
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break;
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case 0x5:
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chip->ecc_strength_ds = 4;
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break;
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case 0x6:
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chip->ecc_strength_ds = 8;
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break;
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default:
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WARN(1, "Could not get ECC info");
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chip->ecc_step_ds = 0;
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break;
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}
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}
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}
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static int toshiba_nand_init(struct nand_chip *chip)
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{
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if (nand_is_slc(chip))
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chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
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return 0;
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}
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const struct nand_manufacturer_ops toshiba_nand_manuf_ops = {
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.detect = toshiba_nand_decode_id,
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.init = toshiba_nand_init,
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};
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