mirror of
https://github.com/AsahiLinux/u-boot
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12e3547f5a
With gcc-11 we see:
drivers/ddr/marvell/a38x/ddr3_debug.c:672:47: error: argument 2 of type 'u32[5]' {aka 'unsigned int[5]'} with mismatched bound [-Werror=array-parameter=]
672 | int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
| ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h:10,
from drivers/ddr/marvell/a38x/ddr3_init.h:17,
from drivers/ddr/marvell/a38x/ddr3_debug.c:6:
drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h:116:47: note: previously declared as 'u32[]' {aka 'unsigned int[]'}
And similar warnings. Correct these by updating the prototype. Remove
the prototype for ddr3_tip_read_pup_value as it is unused.
Signed-off-by: Tom Rini <trini@konsulko.com>
124 lines
4.6 KiB
C
124 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _DDR3_TRAINING_IP_FLOW_H_
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#define _DDR3_TRAINING_IP_FLOW_H_
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#include "ddr3_training_ip.h"
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#include "ddr3_training_ip_db.h"
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#include "mv_ddr_plat.h"
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#define KILLER_PATTERN_LENGTH 32
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#define EXT_ACCESS_BURST_LENGTH 8
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#define ECC_READ_BUS_0 0
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#define ECC_PHY_ACCESS_3 3
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#define ECC_PHY_ACCESS_4 4
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#define ECC_PHY_ACCESS_8 8
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#define BUS_WIDTH_IN_BITS 8
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#define MAX_POLLING_ITERATIONS 1000000
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#define ADLL_LENGTH 32
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#define GP_RSVD0_REG 0x182e0
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/*
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* DFX address Space
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* Table 2: DFX address space
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* Address Bits Value Description
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* [31 : 20] 0x? DFX base address bases PCIe mapping
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* [19 : 15] 0...Number_of_client-1 Client Index inside pipe.
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* See also Table 1 Multi_cast = 29 Broadcast = 28
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* [14 : 13] 2'b01 Access to Client Internal Register
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* [12 : 0] Client Internal Register offset See related Client Registers
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* [14 : 13] 2'b00 Access to Ram Wrappers Internal Register
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* [12 : 6] 0 Number_of_rams-1 Ram Index inside Client
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* [5 : 0] Ram Wrapper Internal Register offset See related Ram Wrappers
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* Registers
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*/
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/* nsec */
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#define AUTO_ZQC_TIMING 15384
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enum mr_number {
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MR_CMD0,
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MR_CMD1,
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MR_CMD2,
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MR_CMD3,
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MR_LAST
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};
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struct mv_ddr_mr_data {
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u32 cmd;
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u32 reg_addr;
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};
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struct write_supp_result {
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enum hws_wl_supp stage;
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int is_pup_fail;
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};
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int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
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enum mv_ddr_freq frequency,
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u32 *round_trip_delay_arr);
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int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
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enum mv_ddr_freq frequency,
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u32 *total_round_trip_delay_arr);
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int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
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u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
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int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
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u32 if_id, u32 exp_value, u32 mask, u32 offset,
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u32 poll_tries);
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int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
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u32 if_id, u32 reg_addr, u32 *data, u32 mask);
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int ddr3_tip_bus_read_modify_write(u32 dev_num,
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enum hws_access_type access_type,
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u32 if_id, u32 phy_id,
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enum hws_ddr_phy phy_type,
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u32 reg_addr, u32 data_value, u32 reg_mask);
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int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access,
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u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
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u32 *data);
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int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access,
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u32 if_id, enum hws_access_type e_phy_access, u32 phy_id,
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enum hws_ddr_phy e_phy_type, u32 reg_addr,
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u32 data_value);
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int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id,
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enum mv_ddr_freq memory_freq);
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int ddr3_tip_adjust_dqs(u32 dev_num);
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int ddr3_tip_init_controller(u32 dev_num);
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int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
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u32 num_of_bursts, u32 *addr);
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int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
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u32 num_of_bursts, u32 *addr);
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int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 ui_freq);
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int mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq);
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int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num);
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int ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 ui_freq);
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int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num);
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int ddr3_tip_dynamic_write_leveling(u32 dev_num, int phase_remove);
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int ddr3_tip_dynamic_write_leveling_supp(u32 dev_num);
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int ddr3_tip_static_init_controller(u32 dev_num);
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int ddr3_tip_configure_phy(u32 dev_num);
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int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
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u32 if_id, enum hws_pattern pattern,
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u32 load_addr);
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int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern e_pattern);
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int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
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u32 if_id, enum hws_dir direction, u32 tx_phases,
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u32 tx_burst_size, u32 rx_phases,
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u32 delay_between_burst, u32 rd_mode, u32 cs_num,
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u32 addr_stress_jump, u32 single_pattern);
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int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask);
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int ddr3_tip_write_cs_result(u32 dev_num, u32 offset);
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int ddr3_tip_reset_fifo_ptr(u32 dev_num);
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int ddr3_tip_read_adll_value(u32 dev_num,
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u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
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u32 reg_addr, u32 mask);
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int ddr3_tip_write_adll_value(u32 dev_num,
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u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
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u32 reg_addr);
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int ddr3_tip_tune_training_params(u32 dev_num, struct tune_train_params *params);
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#endif /* _DDR3_TRAINING_IP_FLOW_H_ */
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