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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
354 lines
7.9 KiB
C
354 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*/
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#include <common.h>
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#include <bitfield.h>
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#include <clk.h>
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#include <cpu.h>
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#include <dm.h>
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#include <log.h>
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#include <vsprintf.h>
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#include <linux/bitops.h>
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#include "mpc83xx_cpu.h"
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/**
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* struct mpc83xx_cpu_priv - Private data for MPC83xx CPUs
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* @e300_type: The e300 core type of the MPC83xx CPU
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* @family: The MPC83xx family the CPU belongs to
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* @type: The MPC83xx type of the CPU
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* @is_e_processor: Flag indicating whether the CPU is a E processor or not
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* @is_a_variant: Flag indicating whtther the CPU is a A variant or not
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* @revid: The revision ID of the CPU
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* @revid.major: The major part of the CPU's revision ID
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* @revid.minor: The minor part of the CPU's revision ID
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*/
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struct mpc83xx_cpu_priv {
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enum e300_type e300_type;
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enum mpc83xx_cpu_family family;
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enum mpc83xx_cpu_type type;
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bool is_e_processor;
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bool is_a_variant;
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struct {
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uint major;
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uint minor;
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} revid;
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};
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int checkcpu(void)
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{
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/* Activate all CPUs from board_f.c */
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return cpu_probe_all();
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}
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/**
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* get_spridr() - Read SPRIDR (System Part and Revision ID Register) of CPU
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*
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* Return: The SPRIDR value
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*/
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static inline u32 get_spridr(void)
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{
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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return in_be32(&immr->sysconf.spridr);
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}
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/**
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* determine_type() - Determine CPU family of MPC83xx device
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* @dev: CPU device from which to read CPU family from
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*/
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static inline void determine_family(const struct udevice *dev)
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{
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struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
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/* Upper 12 bits of PARTID field (bits 0-23 in SPRIDR) */
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const u32 PARTID_FAMILY_MASK = 0xFFF00000;
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switch (bitfield_extract_by_mask(get_spridr(), PARTID_FAMILY_MASK)) {
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case 0x810:
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case 0x811:
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priv->family = FAMILY_830X;
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break;
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case 0x80B:
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priv->family = FAMILY_831X;
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break;
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case 0x806:
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priv->family = FAMILY_832X;
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break;
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case 0x803:
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priv->family = FAMILY_834X;
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break;
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case 0x804:
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priv->family = FAMILY_836X;
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break;
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case 0x80C:
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priv->family = FAMILY_837X;
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break;
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default:
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priv->family = FAMILY_UNKNOWN;
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}
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}
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/**
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* determine_type() - Determine CPU type of MPC83xx device
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* @dev: CPU device from which to read CPU type from
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*/
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static inline void determine_type(const struct udevice *dev)
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{
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struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
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/* Upper 16 bits of PVR (Processor Version Register) */
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const u32 PCR_UPPER_MASK = 0xFFFF0000;
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u32 val;
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val = bitfield_extract_by_mask(get_spridr(), PCR_UPPER_MASK);
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/* Mask out E-variant bit */
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switch (val & 0xFFFE) {
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case 0x8100:
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priv->type = TYPE_8308;
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break;
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case 0x8110:
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priv->type = TYPE_8309;
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break;
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case 0x80B2:
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priv->type = TYPE_8311;
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break;
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case 0x80B0:
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priv->type = TYPE_8313;
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break;
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case 0x80B6:
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priv->type = TYPE_8314;
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break;
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case 0x80B4:
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priv->type = TYPE_8315;
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break;
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case 0x8066:
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priv->type = TYPE_8321;
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break;
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case 0x8062:
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priv->type = TYPE_8323;
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break;
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case 0x8036:
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priv->type = TYPE_8343;
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break;
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case 0x8032:
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priv->type = TYPE_8347_TBGA;
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break;
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case 0x8034:
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priv->type = TYPE_8347_PBGA;
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break;
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case 0x8030:
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priv->type = TYPE_8349;
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break;
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case 0x804A:
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priv->type = TYPE_8358_TBGA;
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break;
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case 0x804E:
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priv->type = TYPE_8358_PBGA;
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break;
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case 0x8048:
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priv->type = TYPE_8360;
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break;
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case 0x80C6:
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priv->type = TYPE_8377;
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break;
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case 0x80C4:
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priv->type = TYPE_8378;
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break;
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case 0x80C2:
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priv->type = TYPE_8379;
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break;
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default:
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priv->type = TYPE_UNKNOWN;
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}
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}
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/**
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* determine_e300_type() - Determine e300 core type of MPC83xx device
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* @dev: CPU device from which to read e300 core type from
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*/
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static inline void determine_e300_type(const struct udevice *dev)
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{
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struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
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/* Upper 16 bits of PVR (Processor Version Register) */
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const u32 PCR_UPPER_MASK = 0xFFFF0000;
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u32 pvr = get_pvr();
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switch ((pvr & PCR_UPPER_MASK) >> 16) {
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case 0x8083:
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priv->e300_type = E300C1;
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break;
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case 0x8084:
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priv->e300_type = E300C2;
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break;
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case 0x8085:
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priv->e300_type = E300C3;
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break;
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case 0x8086:
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priv->e300_type = E300C4;
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break;
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default:
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priv->e300_type = E300_UNKNOWN;
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}
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}
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/**
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* determine_revid() - Determine revision ID of CPU device
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* @dev: CPU device from which to read revision ID
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*/
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static inline void determine_revid(const struct udevice *dev)
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{
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struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
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u32 REVID_MAJOR_MASK;
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u32 REVID_MINOR_MASK;
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u32 spridr = get_spridr();
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if (priv->family == FAMILY_834X) {
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REVID_MAJOR_MASK = 0x0000FF00;
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REVID_MINOR_MASK = 0x000000FF;
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} else {
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REVID_MAJOR_MASK = 0x000000F0;
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REVID_MINOR_MASK = 0x0000000F;
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}
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priv->revid.major = bitfield_extract_by_mask(spridr, REVID_MAJOR_MASK);
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priv->revid.minor = bitfield_extract_by_mask(spridr, REVID_MINOR_MASK);
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}
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/**
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* determine_cpu_data() - Determine CPU information from hardware
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* @dev: CPU device from which to read information
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*/
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static void determine_cpu_data(const struct udevice *dev)
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{
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struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
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const u32 E_FLAG_MASK = 0x00010000;
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u32 spridr = get_spridr();
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determine_family(dev);
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determine_type(dev);
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determine_e300_type(dev);
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determine_revid(dev);
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if ((priv->family == FAMILY_834X ||
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priv->family == FAMILY_836X) && priv->revid.major >= 2)
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priv->is_a_variant = true;
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priv->is_e_processor = !bitfield_extract_by_mask(spridr, E_FLAG_MASK);
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}
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static int mpc83xx_cpu_get_desc(const struct udevice *dev, char *buf, int size)
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{
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struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
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struct clk core_clk;
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struct clk csb_clk;
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char core_freq[32];
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char csb_freq[32];
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int ret;
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ret = clk_get_by_index((struct udevice *)dev, 0, &core_clk);
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if (ret) {
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debug("%s: Failed to get core clock (err = %d)\n",
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dev->name, ret);
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return ret;
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}
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ret = clk_get_by_index((struct udevice *)dev, 1, &csb_clk);
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if (ret) {
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debug("%s: Failed to get CSB clock (err = %d)\n",
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dev->name, ret);
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return ret;
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}
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determine_cpu_data(dev);
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snprintf(buf, size,
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"%s, MPC%s%s%s, Rev: %d.%d at %s MHz, CSB: %s MHz",
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e300_names[priv->e300_type],
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cpu_type_names[priv->type],
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priv->is_e_processor ? "E" : "",
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priv->is_a_variant ? "A" : "",
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priv->revid.major,
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priv->revid.minor,
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strmhz(core_freq, clk_get_rate(&core_clk)),
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strmhz(csb_freq, clk_get_rate(&csb_clk)));
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return 0;
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}
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static int mpc83xx_cpu_get_info(const struct udevice *dev,
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struct cpu_info *info)
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{
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struct clk clock;
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int ret;
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ulong freq;
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ret = clk_get_by_index((struct udevice *)dev, 0, &clock);
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if (ret) {
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debug("%s: Failed to get core clock (err = %d)\n",
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dev->name, ret);
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return ret;
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}
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freq = clk_get_rate(&clock);
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if (!freq) {
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debug("%s: Core clock speed is zero\n", dev->name);
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return -EINVAL;
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}
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info->cpu_freq = freq;
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info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
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return 0;
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}
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static int mpc83xx_cpu_get_count(const struct udevice *dev)
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{
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/* We have one e300cX core */
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return 1;
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}
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static int mpc83xx_cpu_get_vendor(const struct udevice *dev, char *buf,
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int size)
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{
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snprintf(buf, size, "NXP");
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return 0;
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}
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static const struct cpu_ops mpc83xx_cpu_ops = {
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.get_desc = mpc83xx_cpu_get_desc,
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.get_info = mpc83xx_cpu_get_info,
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.get_count = mpc83xx_cpu_get_count,
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.get_vendor = mpc83xx_cpu_get_vendor,
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};
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static int mpc83xx_cpu_probe(struct udevice *dev)
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{
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return 0;
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}
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static const struct udevice_id mpc83xx_cpu_ids[] = {
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{ .compatible = "fsl,mpc83xx", },
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{ .compatible = "fsl,mpc8308", },
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{ .compatible = "fsl,mpc8309", },
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{ .compatible = "fsl,mpc8313", },
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{ .compatible = "fsl,mpc8315", },
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{ .compatible = "fsl,mpc832x", },
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{ .compatible = "fsl,mpc8349", },
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{ .compatible = "fsl,mpc8360", },
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{ .compatible = "fsl,mpc8379", },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(mpc83xx_cpu) = {
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.name = "mpc83xx_cpu",
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.id = UCLASS_CPU,
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.of_match = mpc83xx_cpu_ids,
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.probe = mpc83xx_cpu_probe,
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.priv_auto = sizeof(struct mpc83xx_cpu_priv),
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.ops = &mpc83xx_cpu_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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