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https://github.com/AsahiLinux/u-boot
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2f78eae506
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
116 lines
3.4 KiB
C
116 lines
3.4 KiB
C
/*
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* LayerScape Internal Memory Map
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*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ARCH_FSL_LSCH3_IMMAP_H
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#define __ARCH_FSL_LSCH3_IMMAP_H_
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/* This is chassis generation 3 */
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struct sys_info {
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unsigned long freq_processor[CONFIG_MAX_CPUS];
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unsigned long freq_systembus;
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unsigned long freq_ddrbus;
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unsigned long freq_localbus;
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unsigned long freq_qe;
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#ifdef CONFIG_SYS_DPAA_FMAN
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unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
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#endif
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#ifdef CONFIG_SYS_DPAA_QBMAN
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unsigned long freq_qman;
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#endif
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#ifdef CONFIG_SYS_DPAA_PME
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unsigned long freq_pme;
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#endif
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};
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/* Global Utilities Block */
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struct ccsr_gur {
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u32 porsr1; /* POR status 1 */
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u32 porsr2; /* POR status 2 */
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u8 res_008[0x20-0x8];
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u32 gpporcr1; /* General-purpose POR configuration */
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u32 gpporcr2; /* General-purpose POR configuration 2 */
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u32 dcfg_fusesr; /* Fuse status register */
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u32 gpporcr3;
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u32 gpporcr4;
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u8 res_034[0x70-0x34];
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u32 devdisr; /* Device disable control */
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u32 devdisr2; /* Device disable control 2 */
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u32 devdisr3; /* Device disable control 3 */
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u32 devdisr4; /* Device disable control 4 */
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u32 devdisr5; /* Device disable control 5 */
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u32 devdisr6; /* Device disable control 6 */
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u32 devdisr7; /* Device disable control 7 */
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u8 res_08c[0x90-0x8c];
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u32 coredisru; /* uppper portion for support of 64 cores */
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u32 coredisrl; /* lower portion for support of 64 cores */
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u8 res_098[0xa0-0x98];
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u32 pvr; /* Processor version */
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u32 svr; /* System version */
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u32 mvr; /* Manufacturing version */
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u8 res_0ac[0x100-0xac];
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u32 rcwsr[32]; /* Reset control word status */
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#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
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#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
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#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
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#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
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u8 res_180[0x200-0x180];
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u32 scratchrw[32]; /* Scratch Read/Write */
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u8 res_280[0x300-0x280];
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u32 scratchw1r[4]; /* Scratch Read (Write once) */
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u8 res_310[0x400-0x310];
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u32 bootlocptrl; /* Boot location pointer low-order addr */
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u32 bootlocptrh; /* Boot location pointer high-order addr */
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u8 res_408[0x500-0x408];
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u8 res_500[0x740-0x500]; /* add more registers when needed */
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u32 tp_ityp[64]; /* Topology Initiator Type Register */
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struct {
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u32 upper;
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u32 lower;
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} tp_cluster[3]; /* Core Cluster n Topology Register */
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u8 res_858[0x1000-0x858];
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};
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#define TP_ITYP_AV 0x00000001 /* Initiator available */
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#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
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#define TP_ITYP_TYPE_ARM 0x0
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#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
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#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
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#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
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#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
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#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
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#define TY_ITYP_VER_A7 0x1
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#define TY_ITYP_VER_A53 0x2
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#define TY_ITYP_VER_A57 0x3
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#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
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#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
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#define TP_INIT_PER_CLUSTER 4
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struct ccsr_clk_cluster_group {
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struct {
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u8 res_00[0x10];
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u32 csr;
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u8 res_14[0x20-0x14];
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} hwncsr[3];
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u8 res_60[0x80-0x60];
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struct {
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u32 gsr;
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u8 res_84[0xa0-0x84];
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} pllngsr[3];
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u8 res_e0[0x100-0xe0];
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};
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struct ccsr_clk_ctrl {
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struct {
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u32 csr; /* core cluster n clock control status */
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u8 res_04[0x20-0x04];
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} clkcncsr[8];
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};
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#endif /* __ARCH_FSL_LSCH3_IMMAP_H */
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