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d9c147f371
Previously, 85xx and 86xx boards would display DRAM information on
bootup such as:
...
I2C: ready
DRAM:
Memory controller interleaving enabled: Bank interleaving!
2 GB
FLASH: 256 MB
...
This patch moves the printing of the DRAM controller configuration to a
common board_add_ram_info() function which prints out DDR type, width,
CAS latency, and ECC mode. It also makes the DDR interleaving
information print out in a more sane manner:
...
I2C: ready
DRAM: 2 GB (DDR2, 64-bit, CL=4, ECC on)
DDR Controller Interleaving Mode: bank
FLASH: 256 MB
...
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
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|---|---|---|
| .. | ||
| common_timing_params.h | ||
| ctrl_regs.c | ||
| ddr.h | ||
| ddr1_dimm_params.c | ||
| ddr2_dimm_params.c | ||
| ddr3_dimm_params.c | ||
| lc_common_dimm_params.c | ||
| main.c | ||
| Makefile | ||
| options.c | ||
| util.c | ||