mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 08:31:03 +00:00
69e173eb57
Move this option to Kconfig and tidy up existing boards. Signed-off-by: Simon Glass <sjg@chromium.org>
142 lines
3.9 KiB
C
142 lines
3.9 KiB
C
/**
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* (C) Copyright 2014, Cavium Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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**/
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#ifndef __THUNDERX_88XX_H__
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#define __THUNDERX_88XX_H__
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#define CONFIG_REMAKE_ELF
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#define CONFIG_THUNDERX
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#define CONFIG_SYS_64BIT
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_IDENT_STRING \
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" for Cavium Thunder CN88XX ARM v8 Multi-Core"
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#define CONFIG_BOOTP_VCI_STRING "Diagnostics"
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#define MEM_BASE 0x00500000
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#define CONFIG_COREID_MASK 0xffffff
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#define CONFIG_SYS_FULL_VA
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#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
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#define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \
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PTL2_MEMTYPE(MT_NORMAL) | \
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PTL2_BLOCK_NON_SHARE}, \
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{0x800000000000UL, 0x40000000000UL, \
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PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \
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PTL2_BLOCK_NON_SHARE}, \
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{0x840000000000UL, 0x40000000000UL, \
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PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \
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PTL2_BLOCK_NON_SHARE}, \
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}
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#define CONFIG_SYS_MEM_MAP_SIZE 3
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#define CONFIG_SYS_VA_BITS 48
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#define CONFIG_SYS_PTL2_BITS 42
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#define CONFIG_SYS_BLOCK_SHIFT 29
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#define CONFIG_SYS_PTL1_ENTRIES 64
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#define CONFIG_SYS_PTL2_ENTRIES 8192
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#define CONFIG_SYS_PGTABLE_SIZE \
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((CONFIG_SYS_PTL1_ENTRIES + \
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CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8)
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#define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32)
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#define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16)
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#define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16)
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/* Link Definitions */
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#define CONFIG_SYS_TEXT_BASE 0x00500000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
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/* SMP Spin Table Definitions */
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#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
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#define CONFIG_SYS_MEMTEST_START MEM_BASE
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#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE)
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
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/* PL011 Serial Configuration */
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#define CONFIG_PL01X_SERIAL
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#define CONFIG_PL011_CLOCK 24000000
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#define CONFIG_CONS_INDEX 1
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE (0x801000000000)
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#define GICR_BASE (0x801000002000)
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#define CONFIG_SYS_SERIAL0 0x87e024000000
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#define CONFIG_SYS_SERIAL1 0x87e025000000
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#define CONFIG_BAUDRATE 115200
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/* Command line configuration */
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#define CONFIG_MENU
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/* BOOTP options */
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_PXE
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#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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/* Initial environment variables */
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#define UBOOT_IMG_HEAD_SIZE 0x40
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/* C80000 - 0x40 */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kernel_addr=08007ffc0\0" \
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"fdt_addr=0x94C00000\0" \
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"fdt_high=0x9fffffff\0"
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#define CONFIG_BOOTARGS \
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"console=ttyAMA0,115200n8 " \
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"earlycon=pl011,0x87e024000000 " \
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"debug maxcpus=48 rootwait rw "\
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"root=/dev/sda2 coherent_pool=16M"
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#define CONFIG_BOOTDELAY 5
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/* Do not preserve environment */
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#define CONFIG_ENV_IS_NOWHERE 1
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#define CONFIG_ENV_SIZE 0x1000
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_NO_RELOCATION 1
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#define CONFIG_LIB_RAND
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#define PLL_REF_CLK 50000000 /* 50 MHz */
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#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
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#endif /* __THUNDERX_88XX_H__ */
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