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4051c400c5
This converts 12 usages of this option to the non-SPL form, since there is no SPL_SANDBOX_CLK_CCF defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
265 lines
8 KiB
C
265 lines
8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
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* Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
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*/
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#ifndef __LINUX_CLK_PROVIDER_H
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#define __LINUX_CLK_PROVIDER_H
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <clk-uclass.h>
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struct udevice;
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static inline void clk_dm(ulong id, struct clk *clk)
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{
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if (!IS_ERR(clk))
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clk->id = id;
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}
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/*
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* flags used across common struct clk. these flags should only affect the
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* top-level framework. custom flags for dealing with hardware specifics
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* belong in struct clk_foo
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*
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* Please update clk_flags[] in drivers/clk/clk.c when making changes here!
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*/
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#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
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#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
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#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
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#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
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/* unused */
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#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
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#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
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#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
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#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
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#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
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#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
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#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
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/* parents need enable during gate/ungate, set rate and re-parent */
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#define CLK_OPS_PARENT_ENABLE BIT(12)
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/* duty cycle call may be forwarded to the parent clock */
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#define CLK_DUTY_CYCLE_PARENT BIT(13)
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#define CLK_MUX_INDEX_ONE BIT(0)
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#define CLK_MUX_INDEX_BIT BIT(1)
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#define CLK_MUX_HIWORD_MASK BIT(2)
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#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
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#define CLK_MUX_ROUND_CLOSEST BIT(4)
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struct clk_mux {
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struct clk clk;
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void __iomem *reg;
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u32 *table;
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u32 mask;
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u8 shift;
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u8 flags;
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/*
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* Fields from struct clk_init_data - this struct has been
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* omitted to avoid too deep level of CCF for bootloader
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*/
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const char * const *parent_names;
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u8 num_parents;
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#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
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u32 io_mux_val;
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#endif
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};
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#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
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extern const struct clk_ops clk_mux_ops;
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u8 clk_mux_get_parent(struct clk *clk);
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/**
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* clk_mux_index_to_val() - Convert the parent index to the register value
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*
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* It returns the value to write in the hardware register to output the selected
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* input clock parent.
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*
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* @table: array of register values corresponding to the parent index (optional)
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* @flags: hardware-specific flags
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* @index: parent clock index
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* Return: the register value
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*/
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unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
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struct clk_gate {
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struct clk clk;
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void __iomem *reg;
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u8 bit_idx;
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u8 flags;
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#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
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u32 io_gate_val;
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#endif
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};
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#define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
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#define CLK_GATE_SET_TO_DISABLE BIT(0)
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#define CLK_GATE_HIWORD_MASK BIT(1)
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extern const struct clk_ops clk_gate_ops;
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struct clk *clk_register_gate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate_flags, spinlock_t *lock);
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struct clk_div_table {
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unsigned int val;
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unsigned int div;
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};
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struct clk_divider {
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struct clk clk;
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void __iomem *reg;
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u8 shift;
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u8 width;
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u8 flags;
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const struct clk_div_table *table;
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#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
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u32 io_divider_val;
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#endif
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};
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#define clk_div_mask(width) ((1 << (width)) - 1)
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#define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
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#define CLK_DIVIDER_ONE_BASED BIT(0)
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#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
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#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
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#define CLK_DIVIDER_HIWORD_MASK BIT(3)
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#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
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#define CLK_DIVIDER_READ_ONLY BIT(5)
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#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
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extern const struct clk_ops clk_divider_ops;
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/**
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* clk_divider_get_table_div() - convert the register value to the divider
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*
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* @table: array of register values corresponding to valid dividers
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* @val: value to convert
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* Return: the divider
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*/
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unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
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unsigned int val);
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/**
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* clk_divider_get_table_val() - convert the divider to the register value
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*
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* It returns the value to write in the hardware register to divide the input
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* clock rate by @div.
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*
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* @table: array of register values corresponding to valid dividers
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* @div: requested divider
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* Return: the register value
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*/
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unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
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unsigned int div);
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/**
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* clk_divider_is_valid_div() - check if the divider is valid
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*
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* @table: array of valid dividers (optional)
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* @div: divider to check
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* @flags: hardware-specific flags
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* Return: true if the divider is valid, false otherwise
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*/
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bool clk_divider_is_valid_div(const struct clk_div_table *table,
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unsigned int div, unsigned long flags);
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/**
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* clk_divider_is_valid_table_div - check if the divider is in the @table array
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*
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* @table: array of valid dividers
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* @div: divider to check
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* Return: true if the divider is found in the @table array, false otherwise
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*/
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bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
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unsigned int div);
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unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
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unsigned int val,
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const struct clk_div_table *table,
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unsigned long flags, unsigned long width);
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struct clk_fixed_factor {
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struct clk clk;
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unsigned int mult;
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unsigned int div;
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};
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extern const struct clk_ops clk_fixed_rate_ops;
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#define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
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clk)
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struct clk_fixed_rate {
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struct clk clk;
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unsigned long fixed_rate;
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};
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#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_plat(dev))
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void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
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struct clk_fixed_rate *plat);
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struct clk_composite {
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struct clk clk;
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struct clk_ops ops;
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struct clk *mux;
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struct clk *rate;
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struct clk *gate;
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const struct clk_ops *mux_ops;
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const struct clk_ops *rate_ops;
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const struct clk_ops *gate_ops;
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};
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#define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
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struct clk *clk_register_composite(struct device *dev, const char *name,
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const char * const *parent_names, int num_parents,
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struct clk *mux_clk, const struct clk_ops *mux_ops,
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struct clk *rate_clk, const struct clk_ops *rate_ops,
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struct clk *gate_clk, const struct clk_ops *gate_ops,
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unsigned long flags);
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int clk_register(struct clk *clk, const char *drv_name, const char *name,
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const char *parent_name);
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struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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unsigned int mult, unsigned int div);
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struct clk *clk_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags);
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struct clk *clk_register_mux(struct device *dev, const char *name,
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const char * const *parent_names, u8 num_parents,
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unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_mux_flags);
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struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
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ulong rate);
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const char *clk_hw_get_name(const struct clk *hw);
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ulong clk_generic_get_rate(struct clk *clk);
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struct clk *dev_get_clk_ptr(struct udevice *dev);
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ulong ccf_clk_get_rate(struct clk *clk);
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ulong ccf_clk_set_rate(struct clk *clk, unsigned long rate);
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int ccf_clk_set_parent(struct clk *clk, struct clk *parent);
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int ccf_clk_enable(struct clk *clk);
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int ccf_clk_disable(struct clk *clk);
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extern const struct clk_ops ccf_clk_ops;
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#endif /* __LINUX_CLK_PROVIDER_H */
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