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cdc9dd0750
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.
Ex:
&spi1 {
status = "okay";
};
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
233 lines
5.5 KiB
Text
233 lines
5.5 KiB
Text
/*
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* Xilinx Zynq 7000 DTSI
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* Describes the hardware common to all Zynq 7000-based boards.
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*
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* Copyright (C) 2013 Xilinx, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "xlnx,zynq-7000";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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clocks = <&clkc 3>;
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clock-latency = <1000>;
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operating-points = <
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/* kHz uV */
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666667 1000000
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333334 1000000
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222223 1000000
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>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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clocks = <&clkc 3>;
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};
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 5 4>, <0 6 4>;
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interrupt-parent = <&intc>;
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reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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i2c0: zynq-i2c@e0004000 {
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compatible = "cdns,i2c-r1p10";
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status = "disabled";
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clocks = <&clkc 38>;
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interrupt-parent = <&intc>;
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interrupts = <0 25 4>;
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reg = <0xe0004000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c1: zynq-i2c@e0005000 {
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compatible = "cdns,i2c-r1p10";
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status = "disabled";
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clocks = <&clkc 39>;
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interrupt-parent = <&intc>;
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interrupts = <0 48 4>;
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reg = <0xe0005000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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intc: interrupt-controller@f8f01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0xF8F01000 0x1000>,
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<0xF8F00100 0x100>;
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};
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xF8F02000 0x1000>;
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arm,data-latency = <3 2 2>;
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arm,tag-latency = <2 2 2>;
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cache-unified;
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cache-level = <2>;
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};
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uart0: uart@e0000000 {
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compatible = "xlnx,xuartps";
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status = "disabled";
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clocks = <&clkc 23>, <&clkc 40>;
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clock-names = "ref_clk", "aper_clk";
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reg = <0xE0000000 0x1000>;
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interrupts = <0 27 4>;
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};
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uart1: uart@e0001000 {
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compatible = "xlnx,xuartps";
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status = "disabled";
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clocks = <&clkc 24>, <&clkc 41>;
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clock-names = "ref_clk", "aper_clk";
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reg = <0xE0001000 0x1000>;
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interrupts = <0 50 4>;
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};
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spi0: spi@e0006000 {
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compatible = "xlnx,zynq-spi";
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reg = <0xe0006000 0x1000>;
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status = "disabled";
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interrupt-parent = <&intc>;
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interrupts = <0 26 4>;
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clocks = <&clkc 25>, <&clkc 34>;
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clock-names = "ref_clk", "pclk";
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spi-max-frequency = <166666700>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@e0007000 {
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compatible = "xlnx,zynq-spi";
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reg = <0xe0007000 0x1000>;
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status = "disabled";
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interrupt-parent = <&intc>;
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interrupts = <0 49 4>;
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clocks = <&clkc 26>, <&clkc 35>;
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clock-names = "ref_clk", "pclk";
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spi-max-frequency = <166666700>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gem0: ethernet@e000b000 {
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compatible = "cdns,gem";
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reg = <0xe000b000 0x4000>;
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status = "disabled";
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interrupts = <0 22 4>;
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clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
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clock-names = "pclk", "hclk", "tx_clk";
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};
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gem1: ethernet@e000c000 {
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compatible = "cdns,gem";
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reg = <0xe000c000 0x4000>;
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status = "disabled";
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interrupts = <0 45 4>;
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clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
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clock-names = "pclk", "hclk", "tx_clk";
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};
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sdhci0: ps7-sdhci@e0100000 {
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkc 21>, <&clkc 32>;
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interrupt-parent = <&intc>;
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interrupts = <0 24 4>;
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reg = <0xe0100000 0x1000>;
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} ;
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sdhci1: ps7-sdhci@e0101000 {
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkc 22>, <&clkc 33>;
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interrupt-parent = <&intc>;
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interrupts = <0 47 4>;
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reg = <0xe0101000 0x1000>;
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} ;
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slcr: slcr@f8000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,zynq-slcr", "syscon";
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reg = <0xF8000000 0x1000>;
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ranges;
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clkc: clkc@100 {
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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ps-clk-frequency = <33333333>;
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fclk-enable = <0>;
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
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"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
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"dma", "usb0_aper", "usb1_aper", "gem0_aper",
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"gem1_aper", "sdio0_aper", "sdio1_aper",
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"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
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"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
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"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
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"dbg_trc", "dbg_apb";
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reg = <0x100 0x100>;
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};
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};
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global_timer: timer@f8f00200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xf8f00200 0x20>;
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interrupts = <1 11 0x301>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 4>;
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};
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ttc0: ttc0@f8001000 {
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interrupt-parent = <&intc>;
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interrupts = < 0 10 4 0 11 4 0 12 4 >;
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compatible = "cdns,ttc";
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clocks = <&clkc 6>;
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reg = <0xF8001000 0x1000>;
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};
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ttc1: ttc1@f8002000 {
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interrupt-parent = <&intc>;
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interrupts = < 0 37 4 0 38 4 0 39 4 >;
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compatible = "cdns,ttc";
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clocks = <&clkc 6>;
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reg = <0xF8002000 0x1000>;
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};
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scutimer: scutimer@f8f00600 {
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interrupt-parent = <&intc>;
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interrupts = < 1 13 0x301 >;
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compatible = "arm,cortex-a9-twd-timer";
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reg = < 0xf8f00600 0x20 >;
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clocks = <&clkc 4>;
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} ;
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};
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};
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