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863b4e1b9d
Add QSPI controller dts node in ls1021a.dtsi. Add QSPI slave device dts node in ls1021a-twr.dts and ls1021a-qds.dts. Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
87 lines
1.2 KiB
Text
87 lines
1.2 KiB
Text
/*
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* Freescale ls1021a TWR board device tree source
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*
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* Copyright 2013-2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "ls1021a.dtsi"
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/ {
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model = "LS1021A TWR Board";
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aliases {
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enet2_rgmii_phy = &rgmii_phy1;
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enet0_sgmii_phy = &sgmii_phy2;
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enet1_sgmii_phy = &sgmii_phy0;
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spi0 = &qspi;
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};
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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qflash0: n25q128a13@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR Flash on board */
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ranges = <0x0 0x0 0x60000000 0x08000000>;
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status = "okay";
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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};
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&lpuart0 {
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status = "okay";
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};
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&mdio0 {
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sgmii_phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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sgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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tbi1: tbi-phy@1f {
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reg = <0x1f>;
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device_type = "tbi-phy";
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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