mirror of
https://github.com/AsahiLinux/u-boot
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a7778f8fbe
Before we can send a command we need both the DATI (command inhibit on mmc_dat line) bit and CMDI (command inhibit on mmc_cmd line) are clear. The previous behavior of only checking on DATI was insufficient on some cards and incorrect behavior in any case. This makes the code check for both bits being clear and makes the error print more clear as to what happened. DATI_CMDDIS is removed as it was unused elsewhere in the code and stood for 'DATI is set, cmds are disabled still'. Fix originally spotted by Peter Bigot. Tested-by: Peter A. Bigot <bigotp@acm.org> Tested-by: Robert Nelson <robertcnelson@gmail.com> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Andreas Müller <schnitzeltony@googlemail.com>
516 lines
13 KiB
C
516 lines
13 KiB
C
/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Sukumar Ghorai <s-ghorai@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation's version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <mmc.h>
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#include <part.h>
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#include <i2c.h>
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#include <twl4030.h>
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#include <twl6030.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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/* If we fail after 1 second wait, something is really bad */
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#define MAX_RETRY_MS 1000
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static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
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static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
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unsigned int siz);
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static struct mmc hsmmc_dev[2];
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#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
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static void omap4_vmmc_pbias_config(struct mmc *mmc)
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{
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u32 value = 0;
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struct omap4_sys_ctrl_regs *const ctrl =
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(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
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value = readl(&ctrl->control_pbiaslite);
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value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
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writel(value, &ctrl->control_pbiaslite);
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/* set VMMC to 3V */
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twl6030_power_mmc_init();
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value = readl(&ctrl->control_pbiaslite);
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value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
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writel(value, &ctrl->control_pbiaslite);
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}
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#endif
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unsigned char mmc_board_init(struct mmc *mmc)
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{
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#if defined(CONFIG_TWL4030_POWER)
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twl4030_power_mmc_init();
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#endif
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#if defined(CONFIG_OMAP34XX)
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t2_t *t2_base = (t2_t *)T2_BASE;
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
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PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
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&t2_base->pbias_lite);
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writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
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&t2_base->devconf0);
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writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
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&t2_base->devconf1);
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writel(readl(&prcm_base->fclken1_core) |
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EN_MMC1 | EN_MMC2 | EN_MMC3,
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&prcm_base->fclken1_core);
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writel(readl(&prcm_base->iclken1_core) |
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EN_MMC1 | EN_MMC2 | EN_MMC3,
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&prcm_base->iclken1_core);
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#endif
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#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
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/* PBIAS config needed for MMC1 only */
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if (mmc->block_dev.dev == 0)
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omap4_vmmc_pbias_config(mmc);
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#endif
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return 0;
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}
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void mmc_init_stream(struct hsmmc *mmc_base)
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{
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ulong start;
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writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
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writel(MMC_CMD0, &mmc_base->cmd);
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start = get_timer(0);
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while (!(readl(&mmc_base->stat) & CC_MASK)) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for cc!\n", __func__);
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return;
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}
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}
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writel(CC_MASK, &mmc_base->stat)
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;
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writel(MMC_CMD0, &mmc_base->cmd)
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;
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start = get_timer(0);
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while (!(readl(&mmc_base->stat) & CC_MASK)) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for cc2!\n", __func__);
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return;
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}
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}
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writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
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}
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static int mmc_init_setup(struct mmc *mmc)
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{
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struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
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unsigned int reg_val;
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unsigned int dsor;
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ulong start;
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mmc_board_init(mmc);
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writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
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&mmc_base->sysconfig);
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start = get_timer(0);
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while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for cc2!\n", __func__);
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return TIMEOUT;
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}
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}
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writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
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start = get_timer(0);
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while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for softresetall!\n",
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__func__);
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return TIMEOUT;
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}
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}
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writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
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writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
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&mmc_base->capa);
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reg_val = readl(&mmc_base->con) & RESERVED_MASK;
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writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
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MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
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HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
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dsor = 240;
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mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
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(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
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mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
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(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
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start = get_timer(0);
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while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for ics!\n", __func__);
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return TIMEOUT;
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}
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}
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writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
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writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
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writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
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IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
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&mmc_base->ie);
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mmc_init_stream(mmc_base);
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return 0;
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}
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static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
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unsigned int flags, mmc_stat;
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ulong start;
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start = get_timer(0);
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while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting on cmd inhibit to clear\n",
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__func__);
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return TIMEOUT;
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}
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}
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writel(0xFFFFFFFF, &mmc_base->stat);
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start = get_timer(0);
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while (readl(&mmc_base->stat)) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for stat!\n", __func__);
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return TIMEOUT;
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}
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}
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/*
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* CMDREG
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* CMDIDX[13:8] : Command index
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* DATAPRNT[5] : Data Present Select
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* ENCMDIDX[4] : Command Index Check Enable
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* ENCMDCRC[3] : Command CRC Check Enable
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* RSPTYP[1:0]
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* 00 = No Response
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* 01 = Length 136
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* 10 = Length 48
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* 11 = Length 48 Check busy after response
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*/
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/* Delay added before checking the status of frq change
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* retry not supported by mmc.c(core file)
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*/
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if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
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udelay(50000); /* wait 50 ms */
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if (!(cmd->resp_type & MMC_RSP_PRESENT))
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flags = 0;
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else if (cmd->resp_type & MMC_RSP_136)
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flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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flags = RSP_TYPE_LGHT48B;
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else
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flags = RSP_TYPE_LGHT48;
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/* enable default flags */
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flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
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MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= CCCE_CHECK;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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flags |= CICE_CHECK;
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if (data) {
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if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
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(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
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flags |= (MSBS_MULTIBLK | BCE_ENABLE);
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data->blocksize = 512;
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writel(data->blocksize | (data->blocks << 16),
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&mmc_base->blk);
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} else
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writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
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if (data->flags & MMC_DATA_READ)
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flags |= (DP_DATA | DDIR_READ);
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else
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flags |= (DP_DATA | DDIR_WRITE);
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}
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writel(cmd->cmdarg, &mmc_base->arg);
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writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
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start = get_timer(0);
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do {
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mmc_stat = readl(&mmc_base->stat);
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s : timeout: No status update\n", __func__);
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return TIMEOUT;
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}
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} while (!mmc_stat);
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if ((mmc_stat & IE_CTO) != 0)
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return TIMEOUT;
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else if ((mmc_stat & ERRI_MASK) != 0)
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return -1;
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if (mmc_stat & CC_MASK) {
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writel(CC_MASK, &mmc_base->stat);
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136) {
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/* response type 2 */
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cmd->response[3] = readl(&mmc_base->rsp10);
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cmd->response[2] = readl(&mmc_base->rsp32);
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cmd->response[1] = readl(&mmc_base->rsp54);
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cmd->response[0] = readl(&mmc_base->rsp76);
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} else
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/* response types 1, 1b, 3, 4, 5, 6 */
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cmd->response[0] = readl(&mmc_base->rsp10);
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}
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}
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if (data && (data->flags & MMC_DATA_READ)) {
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mmc_read_data(mmc_base, data->dest,
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data->blocksize * data->blocks);
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} else if (data && (data->flags & MMC_DATA_WRITE)) {
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mmc_write_data(mmc_base, data->src,
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data->blocksize * data->blocks);
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}
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return 0;
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}
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static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
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{
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unsigned int *output_buf = (unsigned int *)buf;
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unsigned int mmc_stat;
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unsigned int count;
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/*
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* Start Polled Read
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*/
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count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
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count /= 4;
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while (size) {
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ulong start = get_timer(0);
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do {
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mmc_stat = readl(&mmc_base->stat);
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for status!\n",
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__func__);
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return TIMEOUT;
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}
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} while (mmc_stat == 0);
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if ((mmc_stat & ERRI_MASK) != 0)
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return 1;
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if (mmc_stat & BRR_MASK) {
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unsigned int k;
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writel(readl(&mmc_base->stat) | BRR_MASK,
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&mmc_base->stat);
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for (k = 0; k < count; k++) {
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*output_buf = readl(&mmc_base->data);
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output_buf++;
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}
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size -= (count*4);
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}
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if (mmc_stat & BWR_MASK)
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writel(readl(&mmc_base->stat) | BWR_MASK,
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&mmc_base->stat);
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if (mmc_stat & TC_MASK) {
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writel(readl(&mmc_base->stat) | TC_MASK,
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&mmc_base->stat);
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break;
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}
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}
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return 0;
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}
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static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
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unsigned int size)
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{
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unsigned int *input_buf = (unsigned int *)buf;
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unsigned int mmc_stat;
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unsigned int count;
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/*
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* Start Polled Read
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*/
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count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
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count /= 4;
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while (size) {
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ulong start = get_timer(0);
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do {
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mmc_stat = readl(&mmc_base->stat);
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for status!\n",
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__func__);
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return TIMEOUT;
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}
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} while (mmc_stat == 0);
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if ((mmc_stat & ERRI_MASK) != 0)
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return 1;
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if (mmc_stat & BWR_MASK) {
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unsigned int k;
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writel(readl(&mmc_base->stat) | BWR_MASK,
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&mmc_base->stat);
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for (k = 0; k < count; k++) {
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writel(*input_buf, &mmc_base->data);
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input_buf++;
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}
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size -= (count*4);
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}
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if (mmc_stat & BRR_MASK)
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writel(readl(&mmc_base->stat) | BRR_MASK,
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&mmc_base->stat);
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if (mmc_stat & TC_MASK) {
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writel(readl(&mmc_base->stat) | TC_MASK,
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&mmc_base->stat);
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break;
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}
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}
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return 0;
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}
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static void mmc_set_ios(struct mmc *mmc)
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{
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struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
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unsigned int dsor = 0;
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ulong start;
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/* configue bus width */
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switch (mmc->bus_width) {
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case 8:
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writel(readl(&mmc_base->con) | DTW_8_BITMODE,
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&mmc_base->con);
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break;
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case 4:
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writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
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&mmc_base->con);
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writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
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&mmc_base->hctl);
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break;
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case 1:
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default:
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writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
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&mmc_base->con);
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writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
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&mmc_base->hctl);
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break;
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}
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/* configure clock with 96Mhz system clock.
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*/
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if (mmc->clock != 0) {
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dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
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if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
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dsor++;
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}
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mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
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(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
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mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
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(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
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start = get_timer(0);
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while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
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if (get_timer(0) - start > MAX_RETRY_MS) {
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printf("%s: timedout waiting for ics!\n", __func__);
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return;
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}
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}
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writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
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}
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int omap_mmc_init(int dev_index)
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{
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struct mmc *mmc;
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mmc = &hsmmc_dev[dev_index];
|
|
|
|
sprintf(mmc->name, "OMAP SD/MMC");
|
|
mmc->send_cmd = mmc_send_cmd;
|
|
mmc->set_ios = mmc_set_ios;
|
|
mmc->init = mmc_init_setup;
|
|
mmc->getcd = NULL;
|
|
|
|
switch (dev_index) {
|
|
case 0:
|
|
mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
|
|
break;
|
|
#ifdef OMAP_HSMMC2_BASE
|
|
case 1:
|
|
mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
|
|
break;
|
|
#endif
|
|
#ifdef OMAP_HSMMC3_BASE
|
|
case 2:
|
|
mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
|
|
break;
|
|
#endif
|
|
default:
|
|
mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
|
|
return 1;
|
|
}
|
|
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
|
|
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
|
|
MMC_MODE_HC;
|
|
|
|
mmc->f_min = 400000;
|
|
mmc->f_max = 52000000;
|
|
|
|
mmc->b_max = 0;
|
|
|
|
#if defined(CONFIG_OMAP34XX)
|
|
/*
|
|
* Silicon revs 2.1 and older do not support multiblock transfers.
|
|
*/
|
|
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
|
|
mmc->b_max = 1;
|
|
#endif
|
|
|
|
mmc_register(mmc);
|
|
|
|
return 0;
|
|
}
|