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d3bcdf838e
Fix NAND FLASH timings for at91sam9x evaluation kits. New timings are based on application note "NAND Flash Support on AT91SAM9 Microcontrollers" available at http://atmel.com/dyn/resources/prod_documents/doc6255.pdf Signed-off-by: Patrice Vilchez <patice.vilchez@atmel.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Stelian Pop <stelian@popies.net>
215 lines
6 KiB
C
215 lines
6 KiB
C
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/at91sam9rl.h>
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#include <asm/arch/at91sam9rl_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <lcd.h>
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#include <atmel_lcdc.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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static void at91sam9rlek_serial_hw_init(void)
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{
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#ifdef CONFIG_USART0
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at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
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at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
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#endif
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#ifdef CONFIG_USART1
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at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
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at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
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#endif
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#ifdef CONFIG_USART2
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at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
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at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
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#endif
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#ifdef CONFIG_USART3 /* DBGU */
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at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
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at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
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#endif
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}
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#ifdef CONFIG_CMD_NAND
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static void at91sam9rlek_nand_hw_init(void)
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{
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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#ifdef CFG_NAND_DBW_16
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AT91_SMC_DBW_16 |
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#else /* CFG_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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#endif
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AT91_SMC_TDF_(2));
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
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/* Configure RDY/BSY */
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at91_set_gpio_input(AT91_PIN_PD17, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(AT91_PIN_PB6, 1);
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at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
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at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
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}
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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static void at91sam9rlek_spi_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PA28, 0); /* SPI0_NPCS0 */
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at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */
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at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */
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at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
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}
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#endif
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#ifdef CONFIG_LCD
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vidinfo_t panel_info = {
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vl_col: 240,
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vl_row: 320,
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vl_clk: 4965000,
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vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
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ATMEL_LCDC_INVFRAME_INVERTED,
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vl_bpix: 3,
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vl_tft: 1,
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vl_hsync_len: 5,
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vl_left_margin: 1,
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vl_right_margin:33,
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vl_vsync_len: 1,
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vl_upper_margin:1,
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vl_lower_margin:0,
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mmio: AT91SAM9RL_LCDC_BASE,
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};
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void lcd_enable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
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}
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static void at91sam9rlek_lcd_hw_init(void)
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{
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at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
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at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
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at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
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at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
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at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
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at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
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at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
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at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
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at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
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at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
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at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
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at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
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at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
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at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
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at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
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at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
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at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
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at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
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at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
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at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
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at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
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gd->fb_base = 0;
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}
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#endif
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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/* arch number of AT91SAM9RLEK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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at91sam9rlek_serial_hw_init();
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#ifdef CONFIG_CMD_NAND
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at91sam9rlek_nand_hw_init();
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91sam9rlek_spi_hw_init();
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#endif
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#ifdef CONFIG_LCD
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at91sam9rlek_lcd_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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