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174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
208 lines
5.1 KiB
C
208 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx window watchdog timer driver.
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*
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* Author(s): Michal Simek <michal.simek@amd.com>
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* Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
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*
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* Copyright (c) 2020, Xilinx Inc.
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <regmap.h>
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#include <wdt.h>
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#include <linux/compat.h>
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#include <dm/device_compat.h>
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#include <linux/io.h>
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/* Refresh Register Masks */
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#define XWT_WWREF_GWRR_MASK BIT(0) /* Refresh and start new period */
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/* Generic Control/Status Register Masks */
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#define XWT_WWCSR_GWEN_MASK BIT(0) /* Enable Bit */
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/* Register offsets for the WWDT device */
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#define XWT_WWDT_MWR_OFFSET 0x00
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#define XWT_WWDT_ESR_OFFSET 0x04
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#define XWT_WWDT_FCR_OFFSET 0x08
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#define XWT_WWDT_FWR_OFFSET 0x0c
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#define XWT_WWDT_SWR_OFFSET 0x10
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#define XWT_WWDT_CNT_MIN 1
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#define XWT_WWDT_CNT_MAX 0xffffffff
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/* Master Write Control Register Masks */
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#define XWT_WWDT_MWR_MASK BIT(0)
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/* Enable and Status Register Masks */
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#define XWT_WWDT_ESR_WINT_MASK BIT(16)
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#define XWT_WWDT_ESR_WSW_MASK BIT(8)
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#define XWT_WWDT_ESR_WEN_MASK BIT(0)
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struct xlnx_wwdt_priv {
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bool enable_once;
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struct regmap *regs;
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struct clk clk;
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};
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struct xlnx_wwdt_plat {
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bool enable_once;
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};
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static int xlnx_wwdt_reset(struct udevice *dev)
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{
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u32 esr;
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struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
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regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK);
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regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr);
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esr |= XWT_WWDT_ESR_WINT_MASK;
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esr &= ~XWT_WWDT_ESR_WSW_MASK;
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regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr);
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regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr);
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esr |= XWT_WWDT_ESR_WSW_MASK;
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regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr);
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return 0;
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}
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static int xlnx_wwdt_stop(struct udevice *dev)
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{
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struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
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if (wdt->enable_once) {
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dev_warn(dev, "Can't stop Xilinx watchdog.\n");
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return -EBUSY;
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}
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/* Disable the window watchdog timer */
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regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK);
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regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK);
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clk_disable(&wdt->clk);
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dev_dbg(dev, "Watchdog disabled!\n");
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return 0;
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}
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static int xlnx_wwdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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{
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int ret;
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u32 esr;
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u64 count, timeout;
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unsigned long clock_f;
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struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
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clock_f = clk_get_rate(&wdt->clk);
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if (IS_ERR_VALUE(clock_f)) {
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dev_err(dev, "failed to get rate\n");
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return clock_f;
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}
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dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f);
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/* Convert timeout from msec to sec */
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timeout = timeout_ms / 1000;
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/* Calculate timeout count */
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count = timeout * clock_f;
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/* Count should be at least 1 */
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if (count < XWT_WWDT_CNT_MIN) {
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debug("%s: watchdog won't fire with 0 ticks\n", __func__);
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count = XWT_WWDT_CNT_MIN;
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}
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/* Limit the count to maximum possible value */
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if (count > XWT_WWDT_CNT_MAX) {
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debug("%s: maximum watchdog timeout exceeded\n", __func__);
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count = XWT_WWDT_CNT_MAX;
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}
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ret = clk_enable(&wdt->clk);
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if (ret) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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/* Disable the window watchdog timer */
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regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK);
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regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK);
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/* Set first window and second window registers with timeout */
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regmap_write(wdt->regs, XWT_WWDT_FWR_OFFSET, 0); /* No pre-timeout */
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regmap_write(wdt->regs, XWT_WWDT_SWR_OFFSET, (u32)count);
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regmap_write(wdt->regs, XWT_WWDT_FCR_OFFSET, 0);
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/* Enable the window watchdog timer */
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regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr);
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esr |= XWT_WWDT_ESR_WEN_MASK;
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regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr);
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return 0;
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}
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static int xlnx_wwdt_expire_now(struct udevice *dev, ulong flags)
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{
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return xlnx_wwdt_start(dev, XWT_WWDT_CNT_MIN, flags);
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}
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static int xlnx_wwdt_probe(struct udevice *dev)
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{
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int ret;
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struct xlnx_wwdt_plat *plat = dev_get_plat(dev);
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struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
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dev_dbg(dev, "%s: Probing wdt%u\n", __func__, dev_seq(dev));
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ret = regmap_init_mem(dev_ofnode(dev), &wdt->regs);
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if (ret) {
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dev_dbg(dev, "failed to get regbase of wwdt\n");
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return ret;
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}
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wdt->enable_once = plat->enable_once;
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ret = clk_get_by_index(dev, 0, &wdt->clk);
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if (ret < 0)
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dev_err(dev, "failed to get clock\n");
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return ret;
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}
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static int xlnx_wwdt_of_to_plat(struct udevice *dev)
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{
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struct xlnx_wwdt_plat *plat = dev_get_plat(dev);
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plat->enable_once = dev_read_u32_default(dev, "xlnx,wdt-enable-once",
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0);
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dev_dbg(dev, "wdt-enable-once %d\n", plat->enable_once);
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return 0;
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}
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static const struct wdt_ops xlnx_wwdt_ops = {
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.start = xlnx_wwdt_start,
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.reset = xlnx_wwdt_reset,
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.stop = xlnx_wwdt_stop,
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.expire_now = xlnx_wwdt_expire_now,
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};
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static const struct udevice_id xlnx_wwdt_ids[] = {
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{ .compatible = "xlnx,versal-wwdt", },
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{ .compatible = "xlnx,versal-wwdt-1.0", }, /* deprecated */
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{},
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};
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U_BOOT_DRIVER(xlnx_wwdt) = {
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.name = "xlnx_wwdt",
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.id = UCLASS_WDT,
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.of_match = xlnx_wwdt_ids,
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.probe = xlnx_wwdt_probe,
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.priv_auto = sizeof(struct xlnx_wwdt_priv),
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.plat_auto = sizeof(struct xlnx_wwdt_plat),
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.of_to_plat = xlnx_wwdt_of_to_plat,
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.ops = &xlnx_wwdt_ops,
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};
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