mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
9d8f78a2a7
It adds the driver for HIFEMAC Ethernet controller found on HiSilicon SoCs like Hi3798MV200. It's based on the mainstream linux driver, but quite a lot of code gets rewritten and cleaned up to adopt u-boot driver model. Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
481 lines
12 KiB
C
481 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Hisilicon Fast Ethernet MAC Driver
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* Adapted from linux
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*
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* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
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* Copyright (c) 2023 Yang Xiwen <forbidden405@outlook.com>
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*/
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#include <dm.h>
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#include <clk.h>
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#include <miiphy.h>
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#include <net.h>
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#include <reset.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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/* MAC control register list */
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#define MAC_PORTSEL 0x0200
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#define MAC_PORTSEL_STAT_CPU BIT(0)
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#define MAC_PORTSEL_RMII BIT(1)
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#define MAC_PORTSET 0x0208
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#define MAC_PORTSET_DUPLEX_FULL BIT(0)
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#define MAC_PORTSET_LINKED BIT(1)
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#define MAC_PORTSET_SPEED_100M BIT(2)
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#define MAC_SET 0x0210
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#define MAX_FRAME_SIZE 1600
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#define MAX_FRAME_SIZE_MASK GENMASK(10, 0)
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#define BIT_PAUSE_EN BIT(18)
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#define RX_COALESCE_SET 0x0340
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#define RX_COALESCED_FRAME_OFFSET 24
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#define RX_COALESCED_FRAMES 8
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#define RX_COALESCED_TIMER 0x74
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#define QLEN_SET 0x0344
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#define RX_DEPTH_OFFSET 8
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#define MAX_HW_FIFO_DEPTH 64
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#define HW_TX_FIFO_DEPTH 1
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#define MAX_HW_RX_FIFO_DEPTH (MAX_HW_FIFO_DEPTH - HW_TX_FIFO_DEPTH)
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#define HW_RX_FIFO_DEPTH min(PKTBUFSRX, MAX_HW_RX_FIFO_DEPTH)
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#define IQFRM_DES 0x0354
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#define RX_FRAME_LEN_MASK GENMASK(11, 0)
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#define RX_FRAME_IN_INDEX_MASK GENMASK(17, 12)
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#define IQ_ADDR 0x0358
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#define EQ_ADDR 0x0360
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#define EQFRM_LEN 0x0364
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#define ADDRQ_STAT 0x036C
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#define TX_CNT_INUSE_MASK GENMASK(5, 0)
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#define BIT_TX_READY BIT(24)
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#define BIT_RX_READY BIT(25)
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/* global control register list */
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#define GLB_HOSTMAC_L32 0x0000
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#define GLB_HOSTMAC_H16 0x0004
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#define GLB_SOFT_RESET 0x0008
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#define SOFT_RESET_ALL BIT(0)
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#define GLB_FWCTRL 0x0010
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#define FWCTRL_VLAN_ENABLE BIT(0)
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#define FWCTRL_FW2CPU_ENA BIT(5)
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#define FWCTRL_FWALL2CPU BIT(7)
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#define GLB_MACTCTRL 0x0014
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#define MACTCTRL_UNI2CPU BIT(1)
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#define MACTCTRL_MULTI2CPU BIT(3)
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#define MACTCTRL_BROAD2CPU BIT(5)
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#define MACTCTRL_MACT_ENA BIT(7)
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#define GLB_IRQ_STAT 0x0030
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#define GLB_IRQ_ENA 0x0034
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#define IRQ_ENA_PORT0_MASK GENMASK(7, 0)
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#define IRQ_ENA_PORT0 BIT(18)
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#define IRQ_ENA_ALL BIT(19)
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#define GLB_IRQ_RAW 0x0038
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#define IRQ_INT_RX_RDY BIT(0)
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#define IRQ_INT_TX_PER_PACKET BIT(1)
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#define IRQ_INT_TX_FIFO_EMPTY BIT(6)
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#define IRQ_INT_MULTI_RXRDY BIT(7)
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#define DEF_INT_MASK (IRQ_INT_MULTI_RXRDY | \
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IRQ_INT_TX_PER_PACKET | \
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IRQ_INT_TX_FIFO_EMPTY)
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#define GLB_MAC_L32_BASE 0x0100
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#define GLB_MAC_H16_BASE 0x0104
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#define MACFLT_HI16_MASK GENMASK(15, 0)
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#define BIT_MACFLT_ENA BIT(17)
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#define BIT_MACFLT_FW2CPU BIT(21)
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#define GLB_MAC_H16(reg) (GLB_MAC_H16_BASE + ((reg) * 0x8))
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#define GLB_MAC_L32(reg) (GLB_MAC_L32_BASE + ((reg) * 0x8))
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#define MAX_MAC_FILTER_NUM 8
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#define MAX_UNICAST_ADDRESSES 2
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#define MAX_MULTICAST_ADDRESSES (MAX_MAC_FILTER_NUM - \
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MAX_UNICAST_ADDRESSES)
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/* software tx and rx queue number, should be power of 2 */
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#define TXQ_NUM 64
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#define RXQ_NUM 128
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#define PHY_RESET_DELAYS_PROPERTY "hisilicon,phy-reset-delays-us"
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#define MAC_RESET_DELAY_PROPERTY "hisilicon,mac-reset-delay-us"
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#define MAC_RESET_ASSERT_PERIOD 200000
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enum phy_reset_delays {
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PRE_DELAY,
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PULSE,
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POST_DELAY,
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DELAYS_NUM,
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};
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enum clk_type {
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CLK_MAC,
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CLK_BUS,
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CLK_PHY,
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CLK_NUM,
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};
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struct hisi_femac_priv {
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void __iomem *port_base;
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void __iomem *glb_base;
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struct clk *clks[CLK_NUM];
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struct reset_ctl *mac_rst;
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struct reset_ctl *phy_rst;
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u32 phy_reset_delays[DELAYS_NUM];
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u32 mac_reset_delay;
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struct phy_device *phy;
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u32 link_status;
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};
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static void hisi_femac_irq_enable(struct hisi_femac_priv *priv, int irqs)
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{
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u32 val;
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val = readl(priv->glb_base + GLB_IRQ_ENA);
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writel(val | irqs, priv->glb_base + GLB_IRQ_ENA);
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}
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static void hisi_femac_irq_disable(struct hisi_femac_priv *priv, int irqs)
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{
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u32 val;
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val = readl(priv->glb_base + GLB_IRQ_ENA);
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writel(val & (~irqs), priv->glb_base + GLB_IRQ_ENA);
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}
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static void hisi_femac_port_init(struct hisi_femac_priv *priv)
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{
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u32 val;
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/* MAC gets link status info and phy mode by software config */
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val = MAC_PORTSEL_STAT_CPU;
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if (priv->phy->interface == PHY_INTERFACE_MODE_RMII)
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val |= MAC_PORTSEL_RMII;
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writel(val, priv->port_base + MAC_PORTSEL);
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/*clear all interrupt status */
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writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
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hisi_femac_irq_disable(priv, IRQ_ENA_PORT0_MASK | IRQ_ENA_PORT0);
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val = readl(priv->glb_base + GLB_FWCTRL);
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val &= ~(FWCTRL_VLAN_ENABLE | FWCTRL_FWALL2CPU);
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val |= FWCTRL_FW2CPU_ENA;
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writel(val, priv->glb_base + GLB_FWCTRL);
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val = readl(priv->glb_base + GLB_MACTCTRL);
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val |= (MACTCTRL_BROAD2CPU | MACTCTRL_MACT_ENA);
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writel(val, priv->glb_base + GLB_MACTCTRL);
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val = readl(priv->port_base + MAC_SET);
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val &= ~MAX_FRAME_SIZE_MASK;
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val |= MAX_FRAME_SIZE;
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writel(val, priv->port_base + MAC_SET);
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val = RX_COALESCED_TIMER |
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(RX_COALESCED_FRAMES << RX_COALESCED_FRAME_OFFSET);
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writel(val, priv->port_base + RX_COALESCE_SET);
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val = (HW_RX_FIFO_DEPTH << RX_DEPTH_OFFSET) | HW_TX_FIFO_DEPTH;
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writel(val, priv->port_base + QLEN_SET);
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}
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static void hisi_femac_rx_refill(struct hisi_femac_priv *priv)
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{
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int i;
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ulong addr;
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for (i = 0; i < HW_RX_FIFO_DEPTH; i++) {
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addr = (ulong)net_rx_packets[i];
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writel(addr, priv->port_base + IQ_ADDR);
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}
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}
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static void hisi_femac_adjust_link(struct udevice *dev)
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{
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struct hisi_femac_priv *priv = dev_get_priv(dev);
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struct phy_device *phy = priv->phy;
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u32 status = 0;
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if (phy->link)
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status |= MAC_PORTSET_LINKED;
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if (phy->duplex == DUPLEX_FULL)
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status |= MAC_PORTSET_DUPLEX_FULL;
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if (phy->speed == SPEED_100)
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status |= MAC_PORTSET_SPEED_100M;
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writel(status, priv->port_base + MAC_PORTSET);
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}
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static int hisi_femac_port_reset(struct hisi_femac_priv *priv)
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{
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u32 val;
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val = readl(priv->glb_base + GLB_SOFT_RESET);
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val |= SOFT_RESET_ALL;
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writel(val, priv->glb_base + GLB_SOFT_RESET);
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udelay(800);
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val &= ~SOFT_RESET_ALL;
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writel(val, priv->glb_base + GLB_SOFT_RESET);
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return 0;
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}
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static int hisi_femac_set_hw_mac_addr(struct udevice *dev)
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{
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struct hisi_femac_priv *priv = dev_get_priv(dev);
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struct eth_pdata *plat = dev_get_plat(dev);
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unsigned char *mac = plat->enetaddr;
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u32 reg;
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reg = mac[1] | (mac[0] << 8);
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writel(reg, priv->glb_base + GLB_HOSTMAC_H16);
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reg = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
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writel(reg, priv->glb_base + GLB_HOSTMAC_L32);
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return 0;
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}
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static int hisi_femac_start(struct udevice *dev)
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{
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int ret;
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struct hisi_femac_priv *priv = dev_get_priv(dev);
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hisi_femac_port_reset(priv);
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hisi_femac_set_hw_mac_addr(dev);
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hisi_femac_rx_refill(priv);
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ret = phy_startup(priv->phy);
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if (ret)
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return log_msg_ret("Failed to startup phy", ret);
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if (!priv->phy->link) {
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debug("%s: link down\n", __func__);
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return -ENODEV;
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}
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hisi_femac_adjust_link(dev);
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writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
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hisi_femac_irq_enable(priv, IRQ_ENA_ALL | IRQ_ENA_PORT0 | DEF_INT_MASK);
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return 0;
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}
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static int hisi_femac_send(struct udevice *dev, void *packet, int length)
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{
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struct hisi_femac_priv *priv = dev_get_priv(dev);
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ulong addr = (ulong)packet;
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int ret;
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// clear previous irq
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writel(IRQ_INT_TX_PER_PACKET, priv->glb_base + GLB_IRQ_RAW);
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// flush cache
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flush_cache(addr, length + ETH_FCS_LEN);
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// write packet address
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writel(addr, priv->port_base + EQ_ADDR);
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// write packet length (and send it)
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writel(length + ETH_FCS_LEN, priv->port_base + EQFRM_LEN);
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// wait until FIFO is empty
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ret = wait_for_bit_le32(priv->glb_base + GLB_IRQ_RAW, IRQ_INT_TX_PER_PACKET, true, 50, false);
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if (ret == -ETIMEDOUT)
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return log_msg_ret("FIFO timeout", ret);
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return 0;
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}
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static int hisi_femac_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct hisi_femac_priv *priv = dev_get_priv(dev);
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int val, index, length;
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val = readl(priv->glb_base + GLB_IRQ_RAW);
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if (!(val & IRQ_INT_RX_RDY))
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return -EAGAIN;
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val = readl(priv->port_base + IQFRM_DES);
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index = (val & RX_FRAME_IN_INDEX_MASK) >> 12;
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length = val & RX_FRAME_LEN_MASK;
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// invalidate cache
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invalidate_dcache_range((ulong)net_rx_packets[index], (ulong)net_rx_packets[index] + length);
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*packetp = net_rx_packets[index];
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// Tell hardware we will process the packet
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writel(IRQ_INT_RX_RDY, priv->glb_base + GLB_IRQ_RAW);
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return length;
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}
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static int hisi_femac_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct hisi_femac_priv *priv = dev_get_priv(dev);
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ulong addr = (ulong)packet;
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// Tell hardware the packet can be reused
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writel(addr, priv->port_base + IQ_ADDR);
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return 0;
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}
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static void hisi_femac_stop(struct udevice *dev)
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{
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struct hisi_femac_priv *priv = dev_get_priv(dev);
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// assert internal reset
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writel(SOFT_RESET_ALL, priv->glb_base + GLB_SOFT_RESET);
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}
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int hisi_femac_of_to_plat(struct udevice *dev)
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{
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int ret, i;
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struct hisi_femac_priv *priv = dev_get_priv(dev);
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static const char * const clk_strs[] = {
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[CLK_MAC] = "mac",
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[CLK_BUS] = "bus",
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[CLK_PHY] = "phy",
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};
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priv->port_base = dev_remap_addr_name(dev, "port");
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if (IS_ERR(priv->port_base))
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return log_msg_ret("Failed to remap port address space", PTR_ERR(priv->port_base));
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priv->glb_base = dev_remap_addr_name(dev, "glb");
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if (IS_ERR(priv->glb_base))
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return log_msg_ret("Failed to remap global address space", PTR_ERR(priv->glb_base));
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for (i = 0; i < ARRAY_SIZE(clk_strs); i++) {
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priv->clks[i] = devm_clk_get(dev, clk_strs[i]);
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if (IS_ERR(priv->clks[i])) {
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dev_err(dev, "Error getting clock %s\n", clk_strs[i]);
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return log_msg_ret("Failed to get clocks", PTR_ERR(priv->clks[i]));
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}
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}
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priv->mac_rst = devm_reset_control_get(dev, "mac");
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if (IS_ERR(priv->mac_rst))
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return log_msg_ret("Failed to get MAC reset", PTR_ERR(priv->mac_rst));
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priv->phy_rst = devm_reset_control_get(dev, "phy");
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if (IS_ERR(priv->phy_rst))
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return log_msg_ret("Failed to get PHY reset", PTR_ERR(priv->phy_rst));
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ret = dev_read_u32_array(dev,
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PHY_RESET_DELAYS_PROPERTY,
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priv->phy_reset_delays,
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DELAYS_NUM);
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if (ret < 0)
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return log_msg_ret("Failed to get PHY reset delays", ret);
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priv->mac_reset_delay = dev_read_u32_default(dev,
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MAC_RESET_DELAY_PROPERTY,
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MAC_RESET_ASSERT_PERIOD);
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return 0;
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}
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static int hisi_femac_phy_reset(struct hisi_femac_priv *priv)
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{
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struct reset_ctl *rst = priv->phy_rst;
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u32 *delays = priv->phy_reset_delays;
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int ret;
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// Disable MAC clk before phy reset
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ret = clk_disable(priv->clks[CLK_MAC]);
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if (ret < 0)
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return log_msg_ret("Failed to disable MAC clock", ret);
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ret = clk_disable(priv->clks[CLK_BUS]);
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if (ret < 0)
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return log_msg_ret("Failed to disable bus clock", ret);
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udelay(delays[PRE_DELAY]);
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ret = reset_assert(rst);
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if (ret < 0)
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return log_msg_ret("Failed to assert reset", ret);
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udelay(delays[PULSE]);
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ret = reset_deassert(rst);
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if (ret < 0)
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return log_msg_ret("Failed to deassert reset", ret);
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udelay(delays[POST_DELAY]);
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ret = clk_enable(priv->clks[CLK_MAC]);
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if (ret < 0)
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return log_msg_ret("Failed to enable MAC clock", ret);
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ret = clk_enable(priv->clks[CLK_BUS]);
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if (ret < 0)
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return log_msg_ret("Failed to enable MAC bus clock", ret);
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return 0;
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}
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int hisi_femac_probe(struct udevice *dev)
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{
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struct hisi_femac_priv *priv = dev_get_priv(dev);
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int ret, i;
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// Enable clocks
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for (i = 0; i < CLK_NUM; i++) {
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ret = clk_prepare_enable(priv->clks[i]);
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if (ret < 0)
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return log_msg_ret("Failed to enable clks", ret);
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}
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// Reset MAC
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ret = reset_assert(priv->mac_rst);
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if (ret < 0)
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return log_msg_ret("Failed to assert MAC reset", ret);
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udelay(priv->mac_reset_delay);
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ret = reset_deassert(priv->mac_rst);
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if (ret < 0)
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return log_msg_ret("Failed to deassert MAC reset", ret);
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// Reset PHY
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ret = hisi_femac_phy_reset(priv);
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if (ret < 0)
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return log_msg_ret("Failed to reset phy", ret);
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// Connect to PHY
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priv->phy = dm_eth_phy_connect(dev);
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if (!priv->phy)
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return log_msg_ret("Failed to connect to phy", -EINVAL);
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hisi_femac_port_init(priv);
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return 0;
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}
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static const struct eth_ops hisi_femac_ops = {
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.start = hisi_femac_start,
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.send = hisi_femac_send,
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.recv = hisi_femac_recv,
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.free_pkt = hisi_femac_free_pkt,
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.stop = hisi_femac_stop,
|
|
.write_hwaddr = hisi_femac_set_hw_mac_addr,
|
|
};
|
|
|
|
static const struct udevice_id hisi_femac_ids[] = {
|
|
{.compatible = "hisilicon,hisi-femac-v1",},
|
|
{.compatible = "hisilicon,hisi-femac-v2",},
|
|
{.compatible = "hisilicon,hi3516cv300-femac",},
|
|
{.compatible = "hisilicon,hi3798mv200-femac",},
|
|
{},
|
|
};
|
|
|
|
U_BOOT_DRIVER(hisi_femac_driver) = {
|
|
.name = "eth_hisi_femac",
|
|
.id = UCLASS_ETH,
|
|
.of_match = of_match_ptr(hisi_femac_ids),
|
|
.of_to_plat = hisi_femac_of_to_plat,
|
|
.ops = &hisi_femac_ops,
|
|
.probe = hisi_femac_probe,
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
.priv_auto = sizeof(struct hisi_femac_priv),
|
|
};
|