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452369cd0c
For the first time since at least the Allwinner A10 SoCs, the D1 (and related cores) use a new pincontroller MMIO register layout, so we cannot use our hardcoded, fixed offsets anymore. Ideally this would all be handled by devicetree and DM drivers, but for the DT-less SPL we still need the legacy interfaces. Add a new Kconfig symbol to differenciate between the two generations of pincontrollers, and just use that to just switch some basic symbols. The rest is already abstracted enough, so works out of the box. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com> Tested-by: Sam Edwards <CFSworks@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
350 lines
8.1 KiB
C
350 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
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*
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* Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c:
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <sunxi_gpio.h>
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/*
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* =======================================================================
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* Low level GPIO/pin controller access functions, to be shared by non-DM
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* SPL code and the DM pinctrl/GPIO drivers.
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* The functions ending in "bank" take a base pointer to a GPIO bank, and
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* the pin offset is relative to that bank.
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* The functions without "bank" in their name take a linear GPIO number,
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* covering all ports, and starting at 0 for PortA.
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* =======================================================================
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*/
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#define GPIO_BANK(pin) ((pin) >> 5)
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#define GPIO_NUM(pin) ((pin) & 0x1f)
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#define GPIO_CFG_REG_OFFSET 0x00
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#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3)
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#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2)
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#define GPIO_DAT_REG_OFFSET 0x10
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#define GPIO_DRV_REG_OFFSET 0x14
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/* Newer SoCs use a slightly different register layout */
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#ifdef CONFIG_SUNXI_NEW_PINCTRL
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/* pin drive strength: 4 bits per pin */
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#define GPIO_DRV_INDEX(pin) ((pin) / 8)
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#define GPIO_DRV_OFFSET(pin) (((pin) % 8) * 4)
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#define GPIO_PULL_REG_OFFSET 0x24
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#else /* older generation pin controllers */
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/* pin drive strength: 2 bits per pin */
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#define GPIO_DRV_INDEX(pin) ((pin) / 16)
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#define GPIO_DRV_OFFSET(pin) (((pin) % 16) * 2)
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#define GPIO_PULL_REG_OFFSET 0x1c
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#endif
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#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4)
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#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
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static void* BANK_TO_GPIO(int bank)
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{
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void *pio_base;
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if (bank < SUNXI_GPIO_L) {
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pio_base = (void *)(uintptr_t)SUNXI_PIO_BASE;
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} else {
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pio_base = (void *)(uintptr_t)SUNXI_R_PIO_BASE;
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bank -= SUNXI_GPIO_L;
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}
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return pio_base + bank * SUNXI_PINCTRL_BANK_SIZE;
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}
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void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val)
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{
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u32 index = GPIO_CFG_INDEX(pin_offset);
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u32 offset = GPIO_CFG_OFFSET(pin_offset);
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clrsetbits_le32(bank_base + GPIO_CFG_REG_OFFSET + index * 4,
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0xfU << offset, val << offset);
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}
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void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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void *pio = BANK_TO_GPIO(bank);
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sunxi_gpio_set_cfgbank(pio, GPIO_NUM(pin), val);
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}
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int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset)
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{
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u32 index = GPIO_CFG_INDEX(pin_offset);
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u32 offset = GPIO_CFG_OFFSET(pin_offset);
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u32 cfg;
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cfg = readl(bank_base + GPIO_CFG_REG_OFFSET + index * 4);
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cfg >>= offset;
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return cfg & 0xf;
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}
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int sunxi_gpio_get_cfgpin(u32 pin)
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{
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u32 bank = GPIO_BANK(pin);
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void *bank_base = BANK_TO_GPIO(bank);
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return sunxi_gpio_get_cfgbank(bank_base, GPIO_NUM(pin));
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}
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static void sunxi_gpio_set_value_bank(void *bank_base, int pin, bool set)
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{
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u32 mask = 1U << pin;
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clrsetbits_le32(bank_base + GPIO_DAT_REG_OFFSET,
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set ? 0 : mask, set ? mask : 0);
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}
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static int sunxi_gpio_get_value_bank(void *bank_base, int pin)
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{
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return !!(readl(bank_base + GPIO_DAT_REG_OFFSET) & (1U << pin));
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}
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void sunxi_gpio_set_drv(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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void *bank_base = BANK_TO_GPIO(bank);
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sunxi_gpio_set_drv_bank(bank_base, GPIO_NUM(pin), val);
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}
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void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val)
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{
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u32 index = GPIO_DRV_INDEX(pin_offset);
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u32 offset = GPIO_DRV_OFFSET(pin_offset);
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clrsetbits_le32(bank_base + GPIO_DRV_REG_OFFSET + index * 4,
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0x3U << offset, val << offset);
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}
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void sunxi_gpio_set_pull(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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void *bank_base = BANK_TO_GPIO(bank);
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sunxi_gpio_set_pull_bank(bank_base, GPIO_NUM(pin), val);
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}
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void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val)
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{
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u32 index = GPIO_PULL_INDEX(pin_offset);
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u32 offset = GPIO_PULL_OFFSET(pin_offset);
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clrsetbits_le32(bank_base + GPIO_PULL_REG_OFFSET + index * 4,
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0x3U << offset, val << offset);
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}
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/* =========== Non-DM code, used by the SPL. ============ */
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#if !CONFIG_IS_ENABLED(DM_GPIO)
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static void sunxi_gpio_set_value(u32 pin, bool set)
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{
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u32 bank = GPIO_BANK(pin);
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void *pio = BANK_TO_GPIO(bank);
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sunxi_gpio_set_value_bank(pio, GPIO_NUM(pin), set);
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}
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static int sunxi_gpio_get_value(u32 pin)
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{
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u32 bank = GPIO_BANK(pin);
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void *pio = BANK_TO_GPIO(bank);
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return sunxi_gpio_get_value_bank(pio, GPIO_NUM(pin));
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}
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int gpio_request(unsigned gpio, const char *label)
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{
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return 0;
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}
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int gpio_free(unsigned gpio)
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{
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return 0;
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}
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int gpio_direction_input(unsigned gpio)
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{
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sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
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return 0;
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}
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int gpio_direction_output(unsigned gpio, int value)
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{
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sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
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sunxi_gpio_set_value(gpio, value);
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return 0;
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}
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int gpio_get_value(unsigned gpio)
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{
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return sunxi_gpio_get_value(gpio);
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}
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int gpio_set_value(unsigned gpio, int value)
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{
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sunxi_gpio_set_value(gpio, value);
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return 0;
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}
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int sunxi_name_to_gpio(const char *name)
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{
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int group = 0;
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int groupsize = 9 * 32;
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long pin;
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char *eptr;
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if (*name == 'P' || *name == 'p')
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name++;
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if (*name >= 'A') {
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group = *name - (*name > 'a' ? 'a' : 'A');
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groupsize = 32;
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name++;
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}
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pin = simple_strtol(name, &eptr, 10);
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if (!*name || *eptr)
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return -1;
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if (pin < 0 || pin > groupsize || group >= 9)
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return -1;
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return group * 32 + pin;
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}
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#endif /* !DM_GPIO */
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/* =========== DM code, used by U-Boot proper. ============ */
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#if CONFIG_IS_ENABLED(DM_GPIO)
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/* TODO(sjg@chromium.org): Remove this function and use device tree */
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int sunxi_name_to_gpio(const char *name)
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{
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unsigned int gpio;
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int ret;
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#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
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char lookup[8];
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if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
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sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
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SUNXI_GPIO_AXP0_VBUS_ENABLE);
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name = lookup;
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}
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#endif
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ret = gpio_lookup_name(name, NULL, NULL, &gpio);
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return ret ? ret : gpio;
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}
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static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct sunxi_gpio_plat *plat = dev_get_plat(dev);
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return sunxi_gpio_get_value_bank(plat->regs, offset);
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}
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static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct sunxi_gpio_plat *plat = dev_get_plat(dev);
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int func;
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func = sunxi_gpio_get_cfgbank(plat->regs, offset);
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if (func == SUNXI_GPIO_OUTPUT)
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return GPIOF_OUTPUT;
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else if (func == SUNXI_GPIO_INPUT)
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return GPIOF_INPUT;
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else
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return GPIOF_FUNC;
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}
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static int sunxi_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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int ret;
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ret = device_get_child(dev, args->args[0], &desc->dev);
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if (ret)
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return ret;
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desc->offset = args->args[1];
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desc->flags = gpio_flags_xlate(args->args[2]);
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return 0;
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}
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static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset,
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ulong flags)
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{
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struct sunxi_gpio_plat *plat = dev_get_plat(dev);
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if (flags & GPIOD_IS_OUT) {
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u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE);
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sunxi_gpio_set_value_bank(plat->regs, offset, value);
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sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
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} else if (flags & GPIOD_IS_IN) {
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u32 pull = 0;
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if (flags & GPIOD_PULL_UP)
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pull = 1;
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else if (flags & GPIOD_PULL_DOWN)
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pull = 2;
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sunxi_gpio_set_pull_bank(plat->regs, offset, pull);
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sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
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}
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return 0;
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}
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static const struct dm_gpio_ops gpio_sunxi_ops = {
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.get_value = sunxi_gpio_get_value,
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.get_function = sunxi_gpio_get_function,
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.xlate = sunxi_gpio_xlate,
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.set_flags = sunxi_gpio_set_flags,
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};
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static int gpio_sunxi_probe(struct udevice *dev)
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{
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struct sunxi_gpio_plat *plat = dev_get_plat(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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/* Tell the uclass how many GPIOs we have */
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if (plat) {
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uc_priv->gpio_count = SUNXI_GPIOS_PER_BANK;
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uc_priv->bank_name = plat->bank_name;
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}
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return 0;
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}
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U_BOOT_DRIVER(gpio_sunxi) = {
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.name = "gpio_sunxi",
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.id = UCLASS_GPIO,
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.probe = gpio_sunxi_probe,
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.ops = &gpio_sunxi_ops,
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};
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#endif /* DM_GPIO */
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