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e1fff66079
The mpc832x has GPIOs handled by the QUICC Engine. The registers are different from the one for the non QE mpc83xx GPIOs. Implement a GPIO driver for those. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
170 lines
3.8 KiB
C
170 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2023 CR GROUP France
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* Christophe Leroy <christophe.leroy@csgroup.eu>
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*/
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#include <common.h>
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#include <dm.h>
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#include <mapmem.h>
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#include <asm/gpio.h>
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#include <asm/immap_83xx.h>
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#include <asm/io.h>
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#include <dm/of_access.h>
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#define QE_DIR_NONE 0
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#define QE_DIR_OUT 1
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#define QE_DIR_IN 2
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#define QE_DIR_IN_OUT 3
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struct qe_gpio_data {
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/* The bank's register base in memory */
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struct gpio_n __iomem *base;
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/* The address of the registers; used to identify the bank */
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phys_addr_t addr;
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};
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static inline u32 gpio_mask(uint gpio)
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{
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return 1U << (31 - (gpio));
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}
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static inline u32 gpio_mask2(uint gpio)
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{
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return 1U << (30 - ((gpio & 15) << 1));
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}
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static int qe_gpio_direction_input(struct udevice *dev, uint gpio)
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{
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struct qe_gpio_data *data = dev_get_priv(dev);
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struct gpio_n __iomem *base = data->base;
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u32 mask2 = gpio_mask2(gpio);
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if (gpio < 16)
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clrsetbits_be32(&base->dir1, mask2 * QE_DIR_OUT, mask2 * QE_DIR_IN);
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else
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clrsetbits_be32(&base->dir2, mask2 * QE_DIR_OUT, mask2 * QE_DIR_IN);
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return 0;
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}
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static int qe_gpio_set_value(struct udevice *dev, uint gpio, int value)
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{
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struct qe_gpio_data *data = dev_get_priv(dev);
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struct gpio_n __iomem *base = data->base;
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u32 mask = gpio_mask(gpio);
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u32 mask2 = gpio_mask2(gpio);
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if (gpio < 16)
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clrsetbits_be32(&base->dir1, mask2 * QE_DIR_IN, mask2 * QE_DIR_OUT);
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else
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clrsetbits_be32(&base->dir2, mask2 * QE_DIR_IN, mask2 * QE_DIR_OUT);
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if (value)
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setbits_be32(&base->pdat, mask);
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else
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clrbits_be32(&base->pdat, mask);
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return 0;
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}
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static int qe_gpio_get_value(struct udevice *dev, uint gpio)
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{
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struct qe_gpio_data *data = dev_get_priv(dev);
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struct gpio_n __iomem *base = data->base;
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u32 mask = gpio_mask(gpio);
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return !!(in_be32(&base->pdat) & mask);
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}
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static int qe_gpio_get_function(struct udevice *dev, uint gpio)
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{
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struct qe_gpio_data *data = dev_get_priv(dev);
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struct gpio_n __iomem *base = data->base;
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u32 mask2 = gpio_mask2(gpio);
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int dir;
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if (gpio < 16)
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dir = in_be32(&base->dir1);
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else
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dir = in_be32(&base->dir2);
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if ((dir & (mask2 * QE_DIR_IN_OUT)) == (mask2 & QE_DIR_IN))
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return GPIOF_INPUT;
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else if ((dir & (mask2 * QE_DIR_IN_OUT)) == (mask2 & QE_DIR_OUT))
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return GPIOF_OUTPUT;
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else
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return GPIOF_UNKNOWN;
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}
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static int qe_gpio_of_to_plat(struct udevice *dev)
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{
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struct qe_gpio_plat *plat = dev_get_plat(dev);
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plat->addr = dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
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return 0;
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}
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static int qe_gpio_plat_to_priv(struct udevice *dev)
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{
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struct qe_gpio_data *priv = dev_get_priv(dev);
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struct qe_gpio_plat *plat = dev_get_plat(dev);
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unsigned long size = plat->size;
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if (size == 0)
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size = sizeof(struct gpio_n);
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priv->addr = plat->addr;
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priv->base = (void __iomem *)plat->addr;
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if (!priv->base)
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return -ENOMEM;
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return 0;
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}
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static int qe_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct qe_gpio_data *data = dev_get_priv(dev);
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char name[32], *str;
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qe_gpio_plat_to_priv(dev);
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snprintf(name, sizeof(name), "QE@%.8llx",
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(unsigned long long)data->addr);
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str = strdup(name);
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if (!str)
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return -ENOMEM;
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uc_priv->bank_name = str;
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uc_priv->gpio_count = 32;
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return 0;
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}
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static const struct dm_gpio_ops gpio_qe_ops = {
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.direction_input = qe_gpio_direction_input,
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.direction_output = qe_gpio_set_value,
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.get_value = qe_gpio_get_value,
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.set_value = qe_gpio_set_value,
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.get_function = qe_gpio_get_function,
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};
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static const struct udevice_id qe_gpio_ids[] = {
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{ .compatible = "fsl,mpc8323-qe-pario-bank"},
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(gpio_qe) = {
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.name = "gpio_qe",
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.id = UCLASS_GPIO,
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.ops = &gpio_qe_ops,
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.of_to_plat = qe_gpio_of_to_plat,
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.plat_auto = sizeof(struct qe_gpio_plat),
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.of_match = qe_gpio_ids,
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.probe = qe_gpio_probe,
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.priv_auto = sizeof(struct qe_gpio_data),
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};
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