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https://github.com/AsahiLinux/u-boot
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58da865e27
According to datasheet, iMX93 has fused parts with CORE1 or NPU or both disabled. So update code to support it, the kernel device tree runtime update will be added in future patches. Signed-off-by: Peng Fan <peng.fan@nxp.com>
310 lines
6.6 KiB
C
310 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <thermal.h>
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#include <asm/global_data.h>
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#include <asm/system.h>
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#include <firmware/imx/sci/sci.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch-imx/cpu.h>
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#include <asm/armv8/cpu.h>
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#include <imx_thermal.h>
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct cpu_imx_plat {
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const char *name;
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const char *rev;
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const char *type;
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u32 cpu_rsrc;
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u32 cpurev;
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u32 freq_mhz;
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u32 mpidr;
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};
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static const char *get_imx_type_str(u32 imxtype)
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{
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switch (imxtype) {
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case MXC_CPU_IMX8QXP:
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case MXC_CPU_IMX8QXP_A0:
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return "8QXP";
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case MXC_CPU_IMX8QM:
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return "8QM";
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case MXC_CPU_IMX93:
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return "93(52)";/* iMX93 Dual core with NPU */
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case MXC_CPU_IMX9351:
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return "93(51)";/* iMX93 Single core with NPU */
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case MXC_CPU_IMX9332:
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return "93(32)";/* iMX93 Dual core without NPU */
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case MXC_CPU_IMX9331:
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return "93(31)";/* iMX93 Single core without NPU */
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case MXC_CPU_IMX9322:
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return "93(22)";/* iMX93 9x9 Dual core */
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case MXC_CPU_IMX9321:
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return "93(21)";/* iMX93 9x9 Single core */
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case MXC_CPU_IMX9312:
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return "93(12)";/* iMX93 9x9 Dual core without NPU */
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case MXC_CPU_IMX9311:
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return "93(11)";/* iMX93 9x9 Single core without NPU */
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default:
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return "??";
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}
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}
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static const char *get_imx_rev_str(u32 rev)
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{
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static char revision[4];
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if (IS_ENABLED(CONFIG_IMX8)) {
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switch (rev) {
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case CHIP_REV_A:
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return "A";
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case CHIP_REV_B:
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return "B";
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case CHIP_REV_C:
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return "C";
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default:
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return "?";
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}
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} else {
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revision[0] = '1' + (((rev & 0xf0) - CHIP_REV_1_0) >> 4);
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revision[1] = '.';
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revision[2] = '0' + (rev & 0xf);
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revision[3] = '\0';
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return revision;
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}
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}
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static void set_core_data(struct udevice *dev)
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{
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struct cpu_imx_plat *plat = dev_get_plat(dev);
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if (device_is_compatible(dev, "arm,cortex-a35")) {
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plat->cpu_rsrc = SC_R_A35;
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plat->name = "A35";
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} else if (device_is_compatible(dev, "arm,cortex-a53")) {
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plat->cpu_rsrc = SC_R_A53;
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plat->name = "A53";
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} else if (device_is_compatible(dev, "arm,cortex-a72")) {
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plat->cpu_rsrc = SC_R_A72;
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plat->name = "A72";
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} else if (device_is_compatible(dev, "arm,cortex-a55")) {
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plat->name = "A55";
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} else {
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plat->cpu_rsrc = SC_R_A53;
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plat->name = "?";
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}
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}
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#if IS_ENABLED(CONFIG_DM_THERMAL)
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static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
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{
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struct udevice *thermal_dev;
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int cpu_tmp, ret;
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int idx = 1; /* use "cpu-thermal0" device */
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if (IS_ENABLED(CONFIG_IMX8)) {
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if (plat->cpu_rsrc == SC_R_A72)
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idx = 2; /* use "cpu-thermal1" device */
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} else {
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idx = 1;
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}
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ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev);
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if (!ret) {
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ret = thermal_get_temp(thermal_dev, &cpu_tmp);
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if (ret)
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return 0xdeadbeef;
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} else {
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return 0xdeadbeef;
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}
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return cpu_tmp;
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}
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#else
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static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
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{
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return 0;
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}
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#endif
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__weak u32 get_cpu_temp_grade(int *minc, int *maxc)
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{
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return 0;
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}
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static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
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{
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struct cpu_imx_plat *plat = dev_get_plat(dev);
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const char *grade;
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int ret, temp;
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int minc, maxc;
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if (size < 100)
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return -ENOSPC;
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ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz",
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plat->type, plat->rev, plat->name, plat->freq_mhz);
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if (IS_ENABLED(CONFIG_IMX9)) {
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switch (get_cpu_temp_grade(&minc, &maxc)) {
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case TEMP_AUTOMOTIVE:
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grade = "Automotive temperature grade ";
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break;
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case TEMP_INDUSTRIAL:
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grade = "Industrial temperature grade ";
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break;
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case TEMP_EXTCOMMERCIAL:
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grade = "Extended Consumer temperature grade ";
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break;
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default:
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grade = "Consumer temperature grade ";
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break;
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}
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buf = buf + ret;
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size = size - ret;
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ret = snprintf(buf, size, "\nCPU: %s (%dC to %dC)", grade, minc, maxc);
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}
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if (IS_ENABLED(CONFIG_DM_THERMAL)) {
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temp = cpu_imx_get_temp(plat);
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buf = buf + ret;
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size = size - ret;
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if (temp != 0xdeadbeef)
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ret = snprintf(buf, size, " at %dC", temp);
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else
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ret = snprintf(buf, size, " - invalid sensor data");
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}
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snprintf(buf + ret, size - ret, "\n");
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return 0;
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}
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static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info)
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{
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struct cpu_imx_plat *plat = dev_get_plat(dev);
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info->cpu_freq = plat->freq_mhz * 1000;
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info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
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return 0;
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}
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static int cpu_imx_get_count(const struct udevice *dev)
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{
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ofnode node;
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int num = 0;
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ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
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const char *device_type;
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if (!ofnode_is_enabled(node))
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continue;
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device_type = ofnode_read_string(node, "device_type");
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if (!device_type)
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continue;
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if (!strcmp(device_type, "cpu"))
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num++;
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}
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return num;
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}
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static int cpu_imx_get_vendor(const struct udevice *dev, char *buf, int size)
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{
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snprintf(buf, size, "NXP");
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return 0;
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}
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static int cpu_imx_is_current(struct udevice *dev)
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{
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struct cpu_imx_plat *plat = dev_get_plat(dev);
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if (plat->mpidr == (read_mpidr() & 0xffff))
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return 1;
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return 0;
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}
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static const struct cpu_ops cpu_imx_ops = {
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.get_desc = cpu_imx_get_desc,
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.get_info = cpu_imx_get_info,
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.get_count = cpu_imx_get_count,
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.get_vendor = cpu_imx_get_vendor,
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.is_current = cpu_imx_is_current,
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};
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static const struct udevice_id cpu_imx_ids[] = {
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{ .compatible = "arm,cortex-a35" },
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{ .compatible = "arm,cortex-a53" },
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{ .compatible = "arm,cortex-a55" },
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{ .compatible = "arm,cortex-a72" },
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{ }
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};
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static ulong imx_get_cpu_rate(struct udevice *dev)
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{
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struct cpu_imx_plat *plat = dev_get_plat(dev);
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struct clk clk;
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ulong rate;
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int ret;
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if (IS_ENABLED(CONFIG_IMX8)) {
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ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU,
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(sc_pm_clock_rate_t *)&rate);
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} else {
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ret = clk_get_by_index(dev, 0, &clk);
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if (!ret) {
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rate = clk_get_rate(&clk);
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if (!rate)
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ret = -EOPNOTSUPP;
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}
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}
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if (ret) {
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printf("Could not read CPU frequency: %d\n", ret);
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return 0;
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}
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return rate;
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}
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static int imx_cpu_probe(struct udevice *dev)
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{
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struct cpu_imx_plat *plat = dev_get_plat(dev);
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u32 cpurev;
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set_core_data(dev);
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cpurev = get_cpu_rev();
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plat->cpurev = cpurev;
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plat->rev = get_imx_rev_str(cpurev & 0xFFF);
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plat->type = get_imx_type_str((cpurev & 0xFF000) >> 12);
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plat->freq_mhz = imx_get_cpu_rate(dev) / 1000000;
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plat->mpidr = dev_read_addr(dev);
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if (plat->mpidr == FDT_ADDR_T_NONE) {
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printf("%s: Failed to get CPU reg property\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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U_BOOT_DRIVER(cpu_imx_drv) = {
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.name = "imx_cpu",
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.id = UCLASS_CPU,
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.of_match = cpu_imx_ids,
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.ops = &cpu_imx_ops,
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.probe = imx_cpu_probe,
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.plat_auto = sizeof(struct cpu_imx_plat),
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.flags = DM_FLAG_PRE_RELOC,
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};
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