mirror of
https://github.com/AsahiLinux/u-boot
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028ab6b598
Add support for the Xilinx ML300 platform * Patch by Stephan Linz, 17 Feb 2004: Fix watchdog support for NIOS * Patch by Josh Fryman, 16 Feb 2004: Fix byte-swapping for cfi_flash.c for different bus widths * Patch by Jon Diekema, 14 Jeb 2004: Remove duplicate "FPGA Support" notes from the README file
207 lines
7.6 KiB
C
207 lines
7.6 KiB
C
/******************************************************************************
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*
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* Author: Xilinx, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
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* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
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* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
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* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
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* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
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* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
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* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
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* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
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* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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*
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* Xilinx hardware products are not intended for use in life support
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* appliances, devices, or systems. Use in such applications is
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* expressly prohibited.
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*
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*
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* (c) Copyright 2002-2004 Xilinx Inc.
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* All rights reserved.
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*
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xemac_i.h
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*
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* This header file contains internal identifiers, which are those shared
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* between XEmac components. The identifiers in this file are not intended for
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* use external to the driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00a rpm 07/31/01 First release
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* 1.00b rpm 02/20/02 Repartitioned files and functions
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* 1.00b rpm 04/29/02 Moved register definitions to xemac_l.h
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* 1.00c rpm 12/05/02 New version includes support for simple DMA
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* </pre>
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*
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******************************************************************************/
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#ifndef XEMAC_I_H /* prevent circular inclusions */
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#define XEMAC_I_H /* by using protection macros */
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/***************************** Include Files *********************************/
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#include "xemac.h"
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#include "xemac_l.h"
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/************************** Constant Definitions *****************************/
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/*
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* Default buffer descriptor control word masks. The default send BD control
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* is set for incrementing the source address by one for each byte transferred,
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* and specify that the destination address (FIFO) is local to the device. The
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* default receive BD control is set for incrementing the destination address
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* by one for each byte transferred, and specify that the source address is
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* local to the device.
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*/
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#define XEM_DFT_SEND_BD_MASK (XDC_DMACR_SOURCE_INCR_MASK | \
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XDC_DMACR_DEST_LOCAL_MASK)
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#define XEM_DFT_RECV_BD_MASK (XDC_DMACR_DEST_INCR_MASK | \
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XDC_DMACR_SOURCE_LOCAL_MASK)
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/*
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* Masks for the IPIF Device Interrupt enable and status registers.
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*/
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#define XEM_IPIF_EMAC_MASK 0x00000004UL /* MAC interrupt */
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#define XEM_IPIF_SEND_DMA_MASK 0x00000008UL /* Send DMA interrupt */
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#define XEM_IPIF_RECV_DMA_MASK 0x00000010UL /* Receive DMA interrupt */
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#define XEM_IPIF_RECV_FIFO_MASK 0x00000020UL /* Receive FIFO interrupt */
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#define XEM_IPIF_SEND_FIFO_MASK 0x00000040UL /* Send FIFO interrupt */
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/*
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* Default IPIF Device Interrupt mask when configured for DMA
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*/
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#define XEM_IPIF_DMA_DFT_MASK (XEM_IPIF_SEND_DMA_MASK | \
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XEM_IPIF_RECV_DMA_MASK | \
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XEM_IPIF_EMAC_MASK | \
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XEM_IPIF_SEND_FIFO_MASK | \
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XEM_IPIF_RECV_FIFO_MASK)
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/*
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* Default IPIF Device Interrupt mask when configured without DMA
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*/
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#define XEM_IPIF_FIFO_DFT_MASK (XEM_IPIF_EMAC_MASK | \
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XEM_IPIF_SEND_FIFO_MASK | \
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XEM_IPIF_RECV_FIFO_MASK)
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#define XEM_IPIF_DMA_DEV_INTR_COUNT 7 /* Number of interrupt sources */
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#define XEM_IPIF_FIFO_DEV_INTR_COUNT 5 /* Number of interrupt sources */
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#define XEM_IPIF_DEVICE_INTR_COUNT 7 /* Number of interrupt sources */
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#define XEM_IPIF_IP_INTR_COUNT 22 /* Number of MAC interrupts */
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/* a mask for all transmit interrupts, used in polled mode */
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#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK | \
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XEM_EIR_XMIT_ERROR_MASK | \
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XEM_EIR_XMIT_SFIFO_EMPTY_MASK | \
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XEM_EIR_XMIT_LFIFO_FULL_MASK)
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/* a mask for all receive interrupts, used in polled mode */
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#define XEM_EIR_RECV_ALL_MASK (XEM_EIR_RECV_DONE_MASK | \
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XEM_EIR_RECV_ERROR_MASK | \
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XEM_EIR_RECV_LFIFO_EMPTY_MASK | \
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XEM_EIR_RECV_LFIFO_OVER_MASK | \
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XEM_EIR_RECV_LFIFO_UNDER_MASK | \
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XEM_EIR_RECV_DFIFO_OVER_MASK | \
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XEM_EIR_RECV_MISSED_FRAME_MASK | \
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XEM_EIR_RECV_COLLISION_MASK | \
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XEM_EIR_RECV_FCS_ERROR_MASK | \
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XEM_EIR_RECV_LEN_ERROR_MASK | \
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XEM_EIR_RECV_SHORT_ERROR_MASK | \
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XEM_EIR_RECV_LONG_ERROR_MASK | \
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XEM_EIR_RECV_ALIGN_ERROR_MASK)
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/* a default interrupt mask for scatter-gather DMA operation */
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#define XEM_EIR_DFT_SG_MASK (XEM_EIR_RECV_ERROR_MASK | \
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XEM_EIR_RECV_LFIFO_OVER_MASK | \
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XEM_EIR_RECV_LFIFO_UNDER_MASK | \
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XEM_EIR_XMIT_SFIFO_OVER_MASK | \
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XEM_EIR_XMIT_SFIFO_UNDER_MASK | \
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XEM_EIR_XMIT_LFIFO_OVER_MASK | \
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XEM_EIR_XMIT_LFIFO_UNDER_MASK | \
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XEM_EIR_RECV_DFIFO_OVER_MASK | \
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XEM_EIR_RECV_MISSED_FRAME_MASK | \
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XEM_EIR_RECV_COLLISION_MASK | \
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XEM_EIR_RECV_FCS_ERROR_MASK | \
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XEM_EIR_RECV_LEN_ERROR_MASK | \
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XEM_EIR_RECV_SHORT_ERROR_MASK | \
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XEM_EIR_RECV_LONG_ERROR_MASK | \
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XEM_EIR_RECV_ALIGN_ERROR_MASK)
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/* a default interrupt mask for non-DMA operation (direct FIFOs) */
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#define XEM_EIR_DFT_FIFO_MASK (XEM_EIR_XMIT_DONE_MASK | \
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XEM_EIR_RECV_DONE_MASK | \
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XEM_EIR_DFT_SG_MASK)
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/*
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* Mask for the DMA interrupt enable and status registers when configured
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* for scatter-gather DMA.
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*/
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#define XEM_DMA_SG_INTR_MASK (XDC_IXR_DMA_ERROR_MASK | \
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XDC_IXR_PKT_THRESHOLD_MASK | \
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XDC_IXR_PKT_WAIT_BOUND_MASK | \
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XDC_IXR_SG_END_MASK)
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/*****************************************************************************/
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/*
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*
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* Clears a structure of given size, in bytes, by setting each byte to 0.
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*
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* @param StructPtr is a pointer to the structure to be cleared.
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* @param NumBytes is the number of bytes in the structure.
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*
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* @return
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*
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* None.
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*
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* @note
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*
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* Signature: void XEmac_mClearStruct(u8 *StructPtr, unsigned int NumBytes)
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*
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******************************************************************************/
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#define XEmac_mClearStruct(StructPtr, NumBytes) \
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{ \
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int i; \
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u8 *BytePtr = (u8 *)(StructPtr); \
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for (i=0; i < (unsigned int)(NumBytes); i++) \
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{ \
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*BytePtr++ = 0; \
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} \
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}
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/************************** Variable Definitions *****************************/
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extern XEmac_Config XEmac_ConfigTable[];
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/************************** Function Prototypes ******************************/
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void XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus);
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void XEmac_CheckFifoRecvError(XEmac * InstancePtr);
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void XEmac_CheckFifoSendError(XEmac * InstancePtr);
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#endif /* end of protection macro */
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