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d865fd0980
-This patchs gives support for the embbedded ppc440 on the Virtex5 FPGAs -interrupts.c divided in uic.c and interrupts.c -xilinx_irq.c for xilinx interrupt controller -Include modifications propossed by Stefan Roese Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
36 lines
1.5 KiB
C
36 lines
1.5 KiB
C
/*
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* (C) Copyright 2008
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* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
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* This work has been supported by: QTechnology http://qtec.com/
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* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef XILINX_IRQ_H
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#define XILINX_IRQ_H
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#define intc XPAR_INTC_0_BASEADDR
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#define ISR (intc+(0*4)) /* Interrupt Status Register */
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#define IPR (intc+(1*4)) /* Interrupt Pending Register */
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#define IER (intc+(2*4)) /* Interrupt Enable Register */
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#define IAR (intc+(3*4)) /* Interrupt Acknowledge Register */
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#define SIE (intc+(4*4)) /* Set Interrupt Enable bits */
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#define CIE (intc+(5*4)) /* Clear Interrupt Enable bits */
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#define IVR (intc+(6*4)) /* Interrupt Vector Register */
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#define MER (intc+(7*4)) /* Master Enable Register */
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#define IRQ_MASK(irq) (1<<(irq&0x1f))
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#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
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#endif
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