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178239de19
This adds multiple i2c channel support for I2C. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
510 lines
12 KiB
C
510 lines
12 KiB
C
/*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* This code should work for both the S3C2400 and the S3C2410
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* as they seem to have the same I2C controller inside.
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* The different address mapping is handled by the s3c24xx.h files below.
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*/
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#include <common.h>
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#ifdef CONFIG_EXYNOS5
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#include <asm/arch/clk.h>
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#include <asm/arch/cpu.h>
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#else
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#include <asm/arch/s3c24x0_cpu.h>
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#endif
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#include <asm/io.h>
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#include <i2c.h>
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#include "s3c24x0_i2c.h"
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#ifdef CONFIG_HARD_I2C
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#define I2C_WRITE 0
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#define I2C_READ 1
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#define I2C_OK 0
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#define I2C_NOK 1
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#define I2C_NACK 2
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#define I2C_NOK_LA 3 /* Lost arbitration */
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#define I2C_NOK_TOUT 4 /* time out */
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#define I2CSTAT_BSY 0x20 /* Busy bit */
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#define I2CSTAT_NACK 0x01 /* Nack bit */
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#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
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#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
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#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
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#define I2C_MODE_MR 0x80 /* Master Receive Mode */
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#define I2C_START_STOP 0x20 /* START / STOP */
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#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
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#define I2C_TIMEOUT 1 /* 1 second */
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static unsigned int g_current_bus; /* Stores Current I2C Bus */
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#ifndef CONFIG_EXYNOS5
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static int GetI2CSDA(void)
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{
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struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
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#ifdef CONFIG_S3C2410
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return (readl(&gpio->gpedat) & 0x8000) >> 15;
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#endif
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#ifdef CONFIG_S3C2400
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return (readl(&gpio->pgdat) & 0x0020) >> 5;
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#endif
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}
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#if 0
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static void SetI2CSDA(int x)
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{
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rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15;
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}
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#endif
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static void SetI2CSCL(int x)
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{
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struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
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#ifdef CONFIG_S3C2410
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writel((readl(&gpio->gpedat) & ~0x4000) |
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(x & 1) << 14, &gpio->gpedat);
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#endif
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#ifdef CONFIG_S3C2400
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writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
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#endif
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}
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#endif
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static int WaitForXfer(struct s3c24x0_i2c *i2c)
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{
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int i;
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i = I2C_TIMEOUT * 10000;
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while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
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udelay(100);
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i--;
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}
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return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
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}
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static int IsACK(struct s3c24x0_i2c *i2c)
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{
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return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
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}
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static void ReadWriteByte(struct s3c24x0_i2c *i2c)
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{
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writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
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}
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static struct s3c24x0_i2c *get_base_i2c(void)
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{
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#ifdef CONFIG_EXYNOS5
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struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
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+ (EXYNOS5_I2C_SPACING
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* g_current_bus));
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return i2c;
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#else
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return s3c24x0_get_base_i2c();
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#endif
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}
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static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
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{
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ulong freq, pres = 16, div;
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#ifdef CONFIG_EXYNOS5
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freq = get_i2c_clk();
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#else
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freq = get_PCLK();
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#endif
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/* calculate prescaler and divisor values */
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if ((freq / pres / (16 + 1)) > speed)
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/* set prescaler to 512 */
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pres = 512;
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div = 0;
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while ((freq / pres / (div + 1)) > speed)
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div++;
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/* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
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writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
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/* init to SLAVE REVEIVE and set slaveaddr */
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writel(0, &i2c->iicstat);
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writel(slaveadd, &i2c->iicadd);
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/* program Master Transmit (and implicit STOP) */
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writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
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}
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/*
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* MULTI BUS I2C support
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*/
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#ifdef CONFIG_I2C_MULTI_BUS
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int i2c_set_bus_num(unsigned int bus)
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{
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struct s3c24x0_i2c *i2c;
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if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {
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debug("Bad bus: %d\n", bus);
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return -1;
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}
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g_current_bus = bus;
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i2c = get_base_i2c();
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i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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return 0;
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}
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unsigned int i2c_get_bus_num(void)
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{
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return g_current_bus;
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}
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#endif
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void i2c_init(int speed, int slaveadd)
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{
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struct s3c24x0_i2c *i2c;
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#ifndef CONFIG_EXYNOS5
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struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
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#endif
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int i;
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/* By default i2c channel 0 is the current bus */
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g_current_bus = 0;
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i2c = get_base_i2c();
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/* wait for some time to give previous transfer a chance to finish */
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i = I2C_TIMEOUT * 1000;
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while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
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udelay(1000);
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i--;
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}
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#ifndef CONFIG_EXYNOS5
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if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
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#ifdef CONFIG_S3C2410
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ulong old_gpecon = readl(&gpio->gpecon);
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#endif
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#ifdef CONFIG_S3C2400
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ulong old_gpecon = readl(&gpio->pgcon);
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#endif
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/* bus still busy probably by (most) previously interrupted
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transfer */
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#ifdef CONFIG_S3C2410
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/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
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writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
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&gpio->gpecon);
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#endif
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#ifdef CONFIG_S3C2400
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/* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
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writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
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&gpio->pgcon);
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#endif
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/* toggle I2CSCL until bus idle */
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SetI2CSCL(0);
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udelay(1000);
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i = 10;
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while ((i > 0) && (GetI2CSDA() != 1)) {
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SetI2CSCL(1);
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udelay(1000);
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SetI2CSCL(0);
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udelay(1000);
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i--;
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}
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SetI2CSCL(1);
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udelay(1000);
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/* restore pin functions */
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#ifdef CONFIG_S3C2410
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writel(old_gpecon, &gpio->gpecon);
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#endif
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#ifdef CONFIG_S3C2400
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writel(old_gpecon, &gpio->pgcon);
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#endif
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}
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#endif /* #ifndef CONFIG_EXYNOS5 */
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i2c_ch_init(i2c, speed, slaveadd);
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}
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/*
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* cmd_type is 0 for write, 1 for read.
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*
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* addr_len can take any value from 0-255, it is only limited
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* by the char, we could make it larger if needed. If it is
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* 0 we skip the address write cycle.
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*/
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static int i2c_transfer(struct s3c24x0_i2c *i2c,
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unsigned char cmd_type,
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unsigned char chip,
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unsigned char addr[],
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unsigned char addr_len,
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unsigned char data[],
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unsigned short data_len)
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{
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int i, result;
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if (data == 0 || data_len == 0) {
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/*Don't support data transfer of no length or to address 0 */
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debug("i2c_transfer: bad call\n");
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return I2C_NOK;
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}
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/* Check I2C bus idle */
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i = I2C_TIMEOUT * 1000;
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while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
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udelay(1000);
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i--;
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}
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if (readl(&i2c->iicstat) & I2CSTAT_BSY)
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return I2C_NOK_TOUT;
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writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
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result = I2C_OK;
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switch (cmd_type) {
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case I2C_WRITE:
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if (addr && addr_len) {
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writel(chip, &i2c->iicds);
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/* send START */
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writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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i = 0;
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while ((i < addr_len) && (result == I2C_OK)) {
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result = WaitForXfer(i2c);
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writel(addr[i], &i2c->iicds);
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ReadWriteByte(i2c);
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i++;
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}
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i = 0;
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while ((i < data_len) && (result == I2C_OK)) {
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result = WaitForXfer(i2c);
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writel(data[i], &i2c->iicds);
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ReadWriteByte(i2c);
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i++;
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}
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} else {
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writel(chip, &i2c->iicds);
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/* send START */
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writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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i = 0;
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while ((i < data_len) && (result = I2C_OK)) {
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result = WaitForXfer(i2c);
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writel(data[i], &i2c->iicds);
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ReadWriteByte(i2c);
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i++;
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}
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}
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if (result == I2C_OK)
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result = WaitForXfer(i2c);
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/* send STOP */
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writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
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ReadWriteByte(i2c);
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break;
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case I2C_READ:
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if (addr && addr_len) {
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writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
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writel(chip, &i2c->iicds);
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/* send START */
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writel(readl(&i2c->iicstat) | I2C_START_STOP,
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&i2c->iicstat);
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result = WaitForXfer(i2c);
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if (IsACK(i2c)) {
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i = 0;
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while ((i < addr_len) && (result == I2C_OK)) {
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writel(addr[i], &i2c->iicds);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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i++;
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}
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writel(chip, &i2c->iicds);
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/* resend START */
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writel(I2C_MODE_MR | I2C_TXRX_ENA |
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I2C_START_STOP, &i2c->iicstat);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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i = 0;
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while ((i < data_len) && (result == I2C_OK)) {
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/* disable ACK for final READ */
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if (i == data_len - 1)
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writel(readl(&i2c->iiccon)
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& ~I2CCON_ACKGEN,
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&i2c->iiccon);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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data[i] = readl(&i2c->iicds);
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i++;
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}
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} else {
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result = I2C_NACK;
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}
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} else {
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writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
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writel(chip, &i2c->iicds);
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/* send START */
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writel(readl(&i2c->iicstat) | I2C_START_STOP,
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&i2c->iicstat);
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result = WaitForXfer(i2c);
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if (IsACK(i2c)) {
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i = 0;
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while ((i < data_len) && (result == I2C_OK)) {
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/* disable ACK for final READ */
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if (i == data_len - 1)
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writel(readl(&i2c->iiccon) &
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~I2CCON_ACKGEN,
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&i2c->iiccon);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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data[i] = readl(&i2c->iicds);
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i++;
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}
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} else {
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result = I2C_NACK;
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}
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}
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/* send STOP */
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writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
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ReadWriteByte(i2c);
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break;
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default:
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debug("i2c_transfer: bad call\n");
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result = I2C_NOK;
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break;
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}
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return result;
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}
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int i2c_probe(uchar chip)
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{
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struct s3c24x0_i2c *i2c;
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uchar buf[1];
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i2c = get_base_i2c();
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buf[0] = 0;
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/*
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* What is needed is to send the chip address and verify that the
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* address was <ACK>ed (i.e. there was a chip at that address which
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* drove the data line low).
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*/
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return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
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}
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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struct s3c24x0_i2c *i2c;
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uchar xaddr[4];
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int ret;
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if (alen > 4) {
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debug("I2C read: addr len %d not supported\n", alen);
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return 1;
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}
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if (alen > 0) {
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xaddr[0] = (addr >> 24) & 0xFF;
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xaddr[1] = (addr >> 16) & 0xFF;
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xaddr[2] = (addr >> 8) & 0xFF;
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xaddr[3] = addr & 0xFF;
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}
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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if (alen > 0)
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chip |= ((addr >> (alen * 8)) &
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CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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#endif
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i2c = get_base_i2c();
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ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen,
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buffer, len);
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if (ret != 0) {
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debug("I2c read: failed %d\n", ret);
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return 1;
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}
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return 0;
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}
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int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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struct s3c24x0_i2c *i2c;
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uchar xaddr[4];
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if (alen > 4) {
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debug("I2C write: addr len %d not supported\n", alen);
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return 1;
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}
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if (alen > 0) {
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xaddr[0] = (addr >> 24) & 0xFF;
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xaddr[1] = (addr >> 16) & 0xFF;
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xaddr[2] = (addr >> 8) & 0xFF;
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xaddr[3] = addr & 0xFF;
|
|
}
|
|
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
|
/*
|
|
* EEPROM chips that implement "address overflow" are ones
|
|
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
|
* address and the extra bits end up in the "chip address"
|
|
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
|
* four 256 byte chips.
|
|
*
|
|
* Note that we consider the length of the address field to
|
|
* still be one byte because the extra address bits are
|
|
* hidden in the chip address.
|
|
*/
|
|
if (alen > 0)
|
|
chip |= ((addr >> (alen * 8)) &
|
|
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
|
#endif
|
|
i2c = get_base_i2c();
|
|
return (i2c_transfer
|
|
(i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
|
|
len) != 0);
|
|
}
|
|
#endif /* CONFIG_HARD_I2C */
|