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https://github.com/AsahiLinux/u-boot
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04cd4e7215
The base address of each DRAM channel can be calculated from other parameters, so does not need hard-coding. What we need is the size of each DRAM channel and DRAM_SPARSE flag to decide the start address of DRAM channel 1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
35 lines
1 KiB
C
35 lines
1 KiB
C
/*
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* Copyright (C) 2011-2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/io.h>
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#include "../init.h"
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#include "bcu-regs.h"
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#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
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void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd)
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{
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int shift;
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writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
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writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
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writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
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writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
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writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
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/* Specify DDR channel */
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shift = bd->dram_ch[0].size / 0x04000000 * 4;
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writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
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shift -= 32;
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writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
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shift -= 32;
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writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
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}
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