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https://github.com/AsahiLinux/u-boot
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253802912a
Introduce the basic am62a7 SoC dtbs from the v6.1-rc3 tag of the linux kernel along with the new am62a specific pinmux definition that we will use to generate the dtbs for the u-boot-spl and u-boot binaries Co-developed-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
103 lines
1.9 KiB
Text
103 lines
1.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM62A7 SoC family in Quad core configuration
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*
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* TRM: https://www.ti.com/lit/zip/spruj16
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*
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* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-am62a.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0: cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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reg = <0x002>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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reg = <0x003>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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};
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x40000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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};
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};
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