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112 lines
3.3 KiB
C
112 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
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/*
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* Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
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*/
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/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0) */
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#define CPU_STM32MP157Cxx 0x05000000
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#define CPU_STM32MP157Axx 0x05000001
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#define CPU_STM32MP153Cxx 0x05000024
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#define CPU_STM32MP153Axx 0x05000025
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#define CPU_STM32MP151Cxx 0x0500002E
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#define CPU_STM32MP151Axx 0x0500002F
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#define CPU_STM32MP157Fxx 0x05000080
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#define CPU_STM32MP157Dxx 0x05000081
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#define CPU_STM32MP153Fxx 0x050000A4
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#define CPU_STM32MP153Dxx 0x050000A5
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#define CPU_STM32MP151Fxx 0x050000AE
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#define CPU_STM32MP151Dxx 0x050000AF
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#define CPU_STM32MP135Cxx 0x05010000
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#define CPU_STM32MP135Axx 0x05010001
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#define CPU_STM32MP133Cxx 0x050100C0
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#define CPU_STM32MP133Axx 0x050100C1
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#define CPU_STM32MP131Cxx 0x050106C8
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#define CPU_STM32MP131Axx 0x050106C9
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#define CPU_STM32MP135Fxx 0x05010800
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#define CPU_STM32MP135Dxx 0x05010801
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#define CPU_STM32MP133Fxx 0x050108C0
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#define CPU_STM32MP133Dxx 0x050108C1
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#define CPU_STM32MP131Fxx 0x05010EC8
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#define CPU_STM32MP131Dxx 0x05010EC9
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/* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */
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#define CPU_STM32MP257Cxx 0x00002000
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#define CPU_STM32MP255Cxx 0x00082000
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#define CPU_STM32MP253Cxx 0x000B2004
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#define CPU_STM32MP251Cxx 0x000B3065
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#define CPU_STM32MP257Axx 0x40002E00
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#define CPU_STM32MP255Axx 0x40082E00
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#define CPU_STM32MP253Axx 0x400B2E04
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#define CPU_STM32MP251Axx 0x400B3E65
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#define CPU_STM32MP257Fxx 0x80002000
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#define CPU_STM32MP255Fxx 0x80082000
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#define CPU_STM32MP253Fxx 0x800B2004
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#define CPU_STM32MP251Fxx 0x800B3065
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#define CPU_STM32MP257Dxx 0xC0002E00
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#define CPU_STM32MP255Dxx 0xC0082E00
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#define CPU_STM32MP253Dxx 0xC00B2E04
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#define CPU_STM32MP251Dxx 0xC00B3E65
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/* return CPU_STMP32MP...Xxx constants */
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u32 get_cpu_type(void);
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#define CPU_DEV_STM32MP15 0x500
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#define CPU_DEV_STM32MP13 0x501
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#define CPU_DEV_STM32MP25 0x505
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/* return CPU_DEV constants */
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u32 get_cpu_dev(void);
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#define CPU_REV1 0x1000
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#define CPU_REV1_1 0x1001
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#define CPU_REV1_2 0x1003
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#define CPU_REV2 0x2000
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#define CPU_REV2_1 0x2001
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#define CPU_REV2_2 0x2003
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/* return Silicon revision = REV_ID[15:0] of Device Version */
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u32 get_cpu_rev(void);
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/* Get Package options from OTP */
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u32 get_cpu_package(void);
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/* package used for STM32MP15x */
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#define STM32MP15_PKG_AA_LBGA448 4
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#define STM32MP15_PKG_AB_LBGA354 3
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#define STM32MP15_PKG_AC_TFBGA361 2
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#define STM32MP15_PKG_AD_TFBGA257 1
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#define STM32MP15_PKG_UNKNOWN 0
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/* package used for STM32MP25x */
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#define STM32MP25_PKG_CUSTOM 0
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#define STM32MP25_PKG_AL_TBGA361 3
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#define STM32MP25_PKG_AK_TBGA424 4
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#define STM32MP25_PKG_AI_TBGA436 5
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#define STM32MP25_PKG_UNKNOWN 7
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/* Get SOC name */
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#define SOC_NAME_SIZE 20
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void get_soc_name(char name[SOC_NAME_SIZE]);
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/* return boot mode */
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u32 get_bootmode(void);
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/* return auth status and partition */
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u32 get_bootauth(void);
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int get_eth_nb(void);
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int setup_mac_address(void);
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/* board power management : configure vddcore according OPP */
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void board_vddcore_init(u32 voltage_mv);
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/* weak function */
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void stm32mp_cpu_init(void);
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void stm32mp_misc_init(void);
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/* helper function: read data from OTP */
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u32 get_otp(int index, int shift, int mask);
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uintptr_t get_stm32mp_rom_api_table(void);
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uintptr_t get_stm32mp_bl2_dtb(void);
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