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https://github.com/AsahiLinux/u-boot
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9938e068fa
Align qspi bindings following kernel dt-bindings Documentation/devicetree/bindings/mtd/stm32-quadspi.txt from kernel v4.17-rc1. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
348 lines
9.2 KiB
Text
348 lines
9.2 KiB
Text
/*
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* Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
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* Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
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*
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* Based on:
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* stm32f429.dtsi from Linux
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* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "armv7-m.dtsi"
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#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
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#include <dt-bindings/clock/stm32fx-clock.h>
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#include <dt-bindings/mfd/stm32f7-rcc.h>
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/ {
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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soc {
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u-boot,dm-pre-reloc;
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mac: ethernet@40028000 {
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compatible = "st,stm32-dwmac";
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reg = <0x40028000 0x8000>;
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reg-names = "stmmaceth";
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
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<&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
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<&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
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interrupts = <61>, <62>;
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interrupt-names = "macirq", "eth_wake_irq";
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snps,pbl = <8>;
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snps,mixed-burst;
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dma-ranges;
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status = "disabled";
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};
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fmc: fmc@A0000000 {
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compatible = "st,stm32-fmc";
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reg = <0xA0000000 0x1000>;
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clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
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u-boot,dm-pre-reloc;
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};
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qspi: quadspi@A0001000 {
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compatible = "st,stm32-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
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reg-names = "qspi", "qspi_mm";
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interrupts = <92>;
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spi-max-frequency = <108000000>;
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clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
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resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
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status = "disabled";
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};
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usart1: serial@40011000 {
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compatible = "st,stm32f7-usart", "st,stm32f7-uart";
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reg = <0x40011000 0x400>;
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interrupts = <37>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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pwrcfg: power-config@58024800 {
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compatible = "syscon";
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reg = <0x40007000 0x400>;
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};
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rcc: rcc@40023810 {
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#reset-cells = <1>;
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#clock-cells = <2>;
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compatible = "st,stm32f746-rcc", "st,stm32-rcc";
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reg = <0x40023800 0x400>;
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clocks = <&clk_hse>;
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st,syscfg = <&pwrcfg>;
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u-boot,dm-pre-reloc;
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};
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pinctrl: pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32f746-pinctrl";
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ranges = <0 0x40020000 0x3000>;
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u-boot,dm-pre-reloc;
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pins-are-numbered;
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gpioa: gpio@40020000 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x0 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
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st,bank-name = "GPIOA";
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u-boot,dm-pre-reloc;
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};
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gpiob: gpio@40020400 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x400 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
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st,bank-name = "GPIOB";
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u-boot,dm-pre-reloc;
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};
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gpioc: gpio@40020800 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x800 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
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st,bank-name = "GPIOC";
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u-boot,dm-pre-reloc;
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};
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gpiod: gpio@40020c00 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0xc00 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
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st,bank-name = "GPIOD";
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u-boot,dm-pre-reloc;
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};
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gpioe: gpio@40021000 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x1000 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
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st,bank-name = "GPIOE";
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u-boot,dm-pre-reloc;
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};
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gpiof: gpio@40021400 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x1400 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
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st,bank-name = "GPIOF";
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u-boot,dm-pre-reloc;
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};
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gpiog: gpio@40021800 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x1800 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
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st,bank-name = "GPIOG";
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u-boot,dm-pre-reloc;
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};
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gpioh: gpio@40021c00 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x1c00 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
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st,bank-name = "GPIOH";
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u-boot,dm-pre-reloc;
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};
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gpioi: gpio@40022000 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x2000 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
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st,bank-name = "GPIOI";
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u-boot,dm-pre-reloc;
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};
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gpioj: gpio@40022400 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x2400 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
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st,bank-name = "GPIOJ";
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u-boot,dm-pre-reloc;
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};
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gpiok: gpio@40022800 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "st,stm32-gpio";
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reg = <0x2800 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
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st,bank-name = "GPIOK";
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u-boot,dm-pre-reloc;
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};
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sdio_pins: sdio_pins@0 {
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pins {
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pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
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<STM32F746_PC9_FUNC_SDMMC1_D1>,
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<STM32F746_PC10_FUNC_SDMMC1_D2>,
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<STM32F746_PC11_FUNC_SDMMC1_D3>,
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<STM32F746_PC12_FUNC_SDMMC1_CK>,
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<STM32F746_PD2_FUNC_SDMMC1_CMD>;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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sdio_pins_od: sdio_pins_od@0 {
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pins1 {
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pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
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<STM32F746_PC9_FUNC_SDMMC1_D1>,
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<STM32F746_PC10_FUNC_SDMMC1_D2>,
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<STM32F746_PC11_FUNC_SDMMC1_D3>,
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<STM32F746_PC12_FUNC_SDMMC1_CK>;
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drive-push-pull;
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slew-rate = <2>;
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};
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pins2 {
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pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
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drive-open-drain;
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slew-rate = <2>;
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};
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};
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sdio_pins_b: sdio_pins_b@0 {
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pins {
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pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
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<STM32F769_PG10_FUNC_SDMMC2_D1>,
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<STM32F769_PB3_FUNC_SDMMC2_D2>,
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<STM32F769_PB4_FUNC_SDMMC2_D3>,
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<STM32F769_PD6_FUNC_SDMMC2_CLK>,
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<STM32F769_PD7_FUNC_SDMMC2_CMD>;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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sdio_pins_od_b: sdio_pins_od_b@0 {
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pins1 {
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pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
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<STM32F769_PG10_FUNC_SDMMC2_D1>,
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<STM32F769_PB3_FUNC_SDMMC2_D2>,
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<STM32F769_PB4_FUNC_SDMMC2_D3>,
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<STM32F769_PD6_FUNC_SDMMC2_CLK>;
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drive-push-pull;
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slew-rate = <2>;
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};
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pins2 {
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pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
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drive-open-drain;
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slew-rate = <2>;
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};
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};
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};
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sdio: sdio@40012c00 {
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compatible = "st,stm32f4xx-sdio";
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reg = <0x40012c00 0x400>;
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clocks = <&rcc 0 171>;
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interrupts = <49>;
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status = "disabled";
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pinctrl-0 = <&sdio_pins>;
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pinctrl-1 = <&sdio_pins_od>;
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pinctrl-names = "default", "opendrain";
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max-frequency = <48000000>;
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};
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sdio2: sdio2@40011c00 {
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compatible = "st,stm32f4xx-sdio";
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reg = <0x40011c00 0x400>;
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clocks = <&rcc 0 167>;
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interrupts = <103>;
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status = "disabled";
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pinctrl-0 = <&sdio_pins_b>;
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pinctrl-1 = <&sdio_pins_od_b>;
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pinctrl-names = "default", "opendrain";
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max-frequency = <48000000>;
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};
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timer5: timer@40000c00 {
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compatible = "st,stm32-timer";
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reg = <0x40000c00 0x400>;
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interrupts = <50>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
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};
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ltdc: display-controller@40016800 {
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compatible = "st,stm32-ltdc";
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reg = <0x40016800 0x200>;
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resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
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u-boot,dm-pre-reloc;
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status = "disabled";
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};
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};
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};
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&systick {
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status = "okay";
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};
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