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e67243f1a3
VOP display endpoint pipeline configuration differs
between rk3288 vs rk3399.
These VOP pipeline configuration depends on how the
different display interfaces connected in sequence to
IN and OUT ports like for,
RK3288:
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopb_out_edp: endpoint@0 {
reg = <0>;
remote-endpoint = <&edp_in_vopb>;
};
vopb_out_hdmi: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_in_vopb>;
};
vopb_out_lvds: endpoint@2 {
reg = <2>;
remote-endpoint = <&lvds_in_vopb>;
};
vopb_out_mipi: endpoint@3 {
reg = <3>;
remote-endpoint = <&mipi_in_vopb>;
};
};
RK3399:
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopb_out_edp: endpoint@0 {
reg = <0>;
remote-endpoint = <&edp_in_vopb>;
};
vopb_out_mipi: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_in_vopb>;
};
vopb_out_hdmi: endpoint@2 {
reg = <2>;
remote-endpoint = <&hdmi_in_vopb>;
};
vopb_out_mipi1: endpoint@3 {
reg = <3>;
remote-endpoint = <&mipi1_in_vopb>;
};
vopb_out_dp: endpoint@4 {
reg = <4>;
remote-endpoint = <&dp_in_vopb>;
};
};
here, HDMI interface has endpoint 1 in rk3288 and 2 in rk3399.
The rockchip vop driver often depends on this determined endpoint
number and stored in vop_mode. So based on this vop_mode the bpp
and pin polarity would configure on detected display interface.
Since, the existing driver using rk3288 vop mode settings enabling
the same will result wrong display interface configuration for rk3399.
Add the patch for fixing these vop modes for rk3399.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
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* Copyright (c) 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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*/
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#include <common.h>
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#include <display.h>
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#include <dm.h>
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#include <regmap.h>
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#include <video.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/io.h>
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#include "rk_vop.h"
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DECLARE_GLOBAL_DATA_PTR;
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static void rk3399_set_pin_polarity(struct udevice *dev,
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enum vop_modes mode, u32 polarity)
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{
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struct rk_vop_priv *priv = dev_get_priv(dev);
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struct rk3288_vop *regs = priv->regs;
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/*
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* The RK3399 VOPs (v3.5 and v3.6) require a per-mode setting of
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* the polarity configuration (in ctrl1).
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*/
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switch (mode) {
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case VOP_MODE_HDMI:
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clrsetbits_le32(®s->dsp_ctrl1,
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M_RK3399_DSP_HDMI_POL,
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V_RK3399_DSP_HDMI_POL(polarity));
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break;
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case VOP_MODE_EDP:
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clrsetbits_le32(®s->dsp_ctrl1,
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M_RK3399_DSP_EDP_POL,
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V_RK3399_DSP_EDP_POL(polarity));
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break;
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case VOP_MODE_MIPI:
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clrsetbits_le32(®s->dsp_ctrl1,
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M_RK3399_DSP_MIPI_POL,
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V_RK3399_DSP_MIPI_POL(polarity));
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break;
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default:
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debug("%s: unsupported output mode %x\n", __func__, mode);
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}
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}
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/*
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* Try some common regulators. We should really get these from the
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* device tree somehow.
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*/
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static const char * const rk3399_regulator_names[] = {
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"vcc33_lcd"
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};
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static int rk3399_vop_probe(struct udevice *dev)
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{
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/* Before relocation we don't need to do anything */
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if (!(gd->flags & GD_FLG_RELOC))
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return 0;
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/* Probe regulators required for the RK3399 VOP */
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rk_vop_probe_regulators(dev, rk3399_regulator_names,
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ARRAY_SIZE(rk3399_regulator_names));
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return rk_vop_probe(dev);
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}
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struct rkvop_driverdata rk3399_lit_driverdata = {
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.set_pin_polarity = rk3399_set_pin_polarity,
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};
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struct rkvop_driverdata rk3399_big_driverdata = {
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.features = VOP_FEATURE_OUTPUT_10BIT,
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.set_pin_polarity = rk3399_set_pin_polarity,
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};
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static const struct udevice_id rk3399_vop_ids[] = {
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{ .compatible = "rockchip,rk3399-vop-big",
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.data = (ulong)&rk3399_big_driverdata },
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{ .compatible = "rockchip,rk3399-vop-lit",
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.data = (ulong)&rk3399_lit_driverdata },
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{ }
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};
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static const struct video_ops rk3399_vop_ops = {
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};
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U_BOOT_DRIVER(rk3399_vop) = {
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.name = "rk3399_vop",
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.id = UCLASS_VIDEO,
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.of_match = rk3399_vop_ids,
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.ops = &rk3399_vop_ops,
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.bind = rk_vop_bind,
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.probe = rk3399_vop_probe,
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.priv_auto_alloc_size = sizeof(struct rk_vop_priv),
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};
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