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GPMC controller on TI's OMAP SoC is general purpose controller to interface with different types of external devices like; - parallel NOR flash - parallel NAND flash - OneNand flash - SDR RAM - Ethernet Devices like LAN9220 Though GPMC configurations may be different for each platform depending on clock-frequency and external device interfacing with controller. But initialization sequence remains common across all platfoms. Thus this patch merges gpmc_init() scattered in different arch-xx/mem.c files into single omap-common/mem-common.c However, actual platforms specific register config values are still sourced from corresponding platform specific headers like; AM33xx: arch/arm/include/asm/arch-am33xx/mem.h OMAP3: arch/arm/include/asm/arch-omap3/mem.h OMAP4: arch/arm/include/asm/arch-omap4/mem.h OMAP4: arch/arm/include/asm/arch-omap5/mem.h Also, CONFIG_xx passed by board-profile decide config for which set of macros need to be used for initialization CONFIG_NAND: initialize GPMC for NAND device CONFIG_NOR: initialize GPMC for NOR device CONFIG_ONENAND: initialize GPMC for ONENAND device Signed-off-by: Pekon Gupta <pekon@ti.com> [trini: define GPMC_SIZE_256M for omap3] Signed-off-by: Tom Rini <trini@ti.com>
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Mansoor Ahamed <mansoor.ahamed@ti.com>
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*
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* Initial Code from:
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* Manikandan Pillai <mani.pillai@ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <command.h>
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#include <linux/mtd/omap_gpmc.h>
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struct gpmc *gpmc_cfg;
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#if defined(CONFIG_OMAP34XX)
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/********************************************************
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* mem_ok() - test used to see if timings are correct
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* for a part. Helps in guessing which part
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* we are currently using.
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*******************************************************/
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u32 mem_ok(u32 cs)
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{
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u32 val1, val2, addr;
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u32 pattern = 0x12345678;
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addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
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writel(0x0, addr + 0x400); /* clear pos A */
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writel(pattern, addr); /* pattern to pos B */
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writel(0x0, addr + 4); /* remove pattern off the bus */
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val1 = readl(addr + 0x400); /* get pos A value */
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val2 = readl(addr); /* get val2 */
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writel(0x0, addr + 0x400); /* clear pos A */
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if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
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return 0;
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else
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return 1;
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}
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#endif
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void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
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u32 size)
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{
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writel(0, &cs->config7);
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sdelay(1000);
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/* Delay for settling */
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writel(gpmc_config[0], &cs->config1);
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writel(gpmc_config[1], &cs->config2);
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writel(gpmc_config[2], &cs->config3);
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writel(gpmc_config[3], &cs->config4);
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writel(gpmc_config[4], &cs->config5);
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writel(gpmc_config[5], &cs->config6);
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/* Enable the config */
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writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
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(1 << 6)), &cs->config7);
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sdelay(2000);
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}
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/*****************************************************
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* gpmc_init(): init gpmc bus
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* Init GPMC for x16, MuxMode (SDRAM in x32).
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* This code can only be executed from SRAM or SDRAM.
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*****************************************************/
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void gpmc_init(void)
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{
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/* putting a blanket check on GPMC based on ZeBu for now */
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gpmc_cfg = (struct gpmc *)GPMC_BASE;
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#if defined(CONFIG_NOR)
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/* configure GPMC for NOR */
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const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
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STNOR_GPMC_CONFIG2,
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STNOR_GPMC_CONFIG3,
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STNOR_GPMC_CONFIG4,
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STNOR_GPMC_CONFIG5,
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STNOR_GPMC_CONFIG6,
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STNOR_GPMC_CONFIG7
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};
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u32 size = GPMC_SIZE_16M;
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u32 base = CONFIG_SYS_FLASH_BASE;
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#elif defined(CONFIG_NAND)
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/* configure GPMC for NAND */
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const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
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M_NAND_GPMC_CONFIG2,
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M_NAND_GPMC_CONFIG3,
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M_NAND_GPMC_CONFIG4,
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M_NAND_GPMC_CONFIG5,
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M_NAND_GPMC_CONFIG6,
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0
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};
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u32 size = GPMC_SIZE_256M;
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u32 base = CONFIG_SYS_NAND_BASE;
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#elif defined(CONFIG_CMD_ONENAND)
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const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1,
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ONENAND_GPMC_CONFIG2,
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ONENAND_GPMC_CONFIG3,
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ONENAND_GPMC_CONFIG4,
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ONENAND_GPMC_CONFIG5,
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ONENAND_GPMC_CONFIG6,
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0
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};
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u32 base = PISMO1_ONEN_BASE;
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u32 size = PISMO1_ONEN_SIZE;
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#else
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const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
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u32 size = 0;
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u32 base = 0;
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#endif
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/* global settings */
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writel(0x00000008, &gpmc_cfg->sysconfig);
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writel(0x00000000, &gpmc_cfg->irqstatus);
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writel(0x00000000, &gpmc_cfg->irqenable);
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writel(0x00000000, &gpmc_cfg->timeout_control);
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#ifdef CONFIG_NOR
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writel(0x00000200, &gpmc_cfg->config);
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#else
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writel(0x00000012, &gpmc_cfg->config);
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#endif
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/*
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* Disable the GPMC0 config set by ROM code
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*/
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writel(0, &gpmc_cfg->cs[0].config7);
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sdelay(1000);
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/* enable chip-select specific configurations */
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enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
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}
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