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NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
27 lines
694 B
Text
27 lines
694 B
Text
#
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# Copyright 2018 NXP
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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NXP LayerScape with Chassis Generation 3.2
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This architecture supports NXP ARMv8 SoCs with Chassis generation 3.2
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for example LX2160A.
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This architecture is enhancement over Chassis Generation 3 with
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few differences mentioned below
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1)DDR Layout
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============
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Entire DDR region splits into three regions.
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- Region 1 is at address 0x8000_0000 to 0xffff_ffff.
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- Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff,
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- Region 3 is at address 0x60_0000_0000 to the top of memory,
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for example 140GB, 0x63_7fff_ffff.
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All DDR memory is marked as cache-enabled.
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2)IFC is removed
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3)Number of I2C controllers increased to 8
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