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https://github.com/AsahiLinux/u-boot
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dc7e5f190d
Activate cache on DDR to improve the accesses to DDR used by SPL: - CONFIG_SPL_BSS_START_ADDR - CONFIG_SYS_SPL_MALLOC_START Cache is configured only when DDR is fully initialized, to avoid speculative access and issue in get_ram_size(). Data cache is deactivated at the end of SPL, to flush the data cache and the TLB. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
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arc | ||
arm | ||
m68k | ||
microblaze | ||
mips | ||
nds32 | ||
nios2 | ||
powerpc | ||
riscv | ||
sandbox | ||
sh | ||
x86 | ||
xtensa | ||
.gitignore | ||
Kconfig | ||
u-boot-elf.lds |