mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-27 15:12:21 +00:00
d702b0811d
The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c
int cleanup_before_linux(void)
{
...
...
dcache_disable();
v7_outer_cache_disable();
invalidate_dcache_all();
}
1) invalidate_dcache_all call expects that all the caches has been
flushed, invalidated and there are no dirty entries prior to its
execution. In the above sequence dcache_disable() flushes, invalidates
the caches and turns off the mmu. But after it cleanups the cache
and before the mmu is disabled there is a cp_delay() function which
has STR instruction. On certain cores like the cortex-a15, cache hit
and a write can happen to a cache line even when the dcache is
disabled. So the above mentioned STR instruction creates a dirty entry
after cleaning. The mmu gets disabled after this.
2) invalidate_dcache_all invalidates the cache lines. Again on
cores like cortex-a15, invalidate instruction flushes the dirty
line as well. So some times the dirty line from sequence 1
can corrupt the memory resulting in a crash.
Fixing this by moving the get_cr() and cp_delay() calls before
cleaning up the cache, thus avoiding the dirty entry.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
|
||
|---|---|---|
| .. | ||
| _ashldi3.S | ||
| _ashrdi3.S | ||
| _divsi3.S | ||
| _lshrdi3.S | ||
| _modsi3.S | ||
| _udivsi3.S | ||
| _umodsi3.S | ||
| board.c | ||
| bootm.c | ||
| cache-cp15.c | ||
| cache-pl310.c | ||
| cache.c | ||
| div0.c | ||
| eabi_compat.c | ||
| interrupts.c | ||
| Makefile | ||
| memcpy.S | ||
| memset.S | ||
| reset.c | ||