mirror of
https://github.com/AsahiLinux/u-boot
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28f40d4a4d
The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
44 lines
955 B
C
44 lines
955 B
C
/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/io.h>
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#include <mach/init.h>
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#include <mach/sc-regs.h>
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void ph1_pro5_clk_init(void)
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{
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u32 tmp;
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/* deassert reset */
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tmp = readl(SC_RSTCTRL);
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#ifdef CONFIG_USB_XHCI_UNIPHIER
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tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
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#endif
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#ifdef CONFIG_NAND_DENALI
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tmp |= SC_RSTCTRL_NRST_NAND;
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#endif
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writel(tmp, SC_RSTCTRL);
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readl(SC_RSTCTRL); /* dummy read */
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#ifdef CONFIG_USB_XHCI_UNIPHIER
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tmp = readl(SC_RSTCTRL2);
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tmp |= SC_RSTCTRL2_NRST_USB3B1;
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writel(tmp, SC_RSTCTRL2);
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readl(SC_RSTCTRL2); /* dummy read */
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#endif
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/* privide clocks */
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tmp = readl(SC_CLKCTRL);
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#ifdef CONFIG_USB_XHCI_UNIPHIER
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tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
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SC_CLKCTRL_CEN_GIO;
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#endif
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#ifdef CONFIG_NAND_DENALI
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tmp |= SC_CLKCTRL_CEN_NAND;
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#endif
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writel(tmp, SC_CLKCTRL);
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readl(SC_CLKCTRL); /* dummy read */
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}
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