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https://github.com/AsahiLinux/u-boot
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527cd43d75
This patch fix the compilation warning
w+../drivers/net/xilinx_ll_temac.c: In function 'll_temac_init':
w+../drivers/net/xilinx_ll_temac.c:235:3: warning: format '%X' expects
argument of type 'unsigned int', but argument 4 has type 'phys_addr_t'
[-Wformat]
introduced by
"net: Declare physical address as phys_addr_t unsigned type"
(sha1: 16ae782722
).
Reported-by: Tom Rini <trini@ti.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
402 lines
9.7 KiB
C
402 lines
9.7 KiB
C
/*
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* Xilinx xps_ll_temac ethernet driver for u-boot
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*
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* supports SDMA or FIFO access and MDIO bus communication
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*
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* Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
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* Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2008 - 2011 PetaLogix
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*
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* Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver
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* Copyright (C) 2008 Nissin Systems Co.,Ltd.
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* March 2008 created
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* [0]: http://www.xilinx.com/support/documentation
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*
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* [S]: [0]/ip_documentation/xps_ll_temac.pdf
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* [A]: [0]/application_notes/xapp1041.pdf
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*/
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#include <config.h>
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#include <common.h>
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#include <net.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include "xilinx_ll_temac.h"
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#include "xilinx_ll_temac_fifo.h"
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#include "xilinx_ll_temac_sdma.h"
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#include "xilinx_ll_temac_mdio.h"
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#if !defined(CONFIG_MII)
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# error "LL_TEMAC requires MII -- missing CONFIG_MII"
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#endif
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#if !defined(CONFIG_PHYLIB)
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# error "LL_TEMAC requires PHYLIB -- missing CONFIG_PHYLIB"
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#endif
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struct ll_temac_info {
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int flags;
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unsigned long base_addr;
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unsigned long ctrl_addr;
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char *devname;
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unsigned int phyaddr;
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char *mdio_busname;
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};
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/* Ethernet interface ready status */
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int ll_temac_check_status(struct temac_reg *regs, u32 mask)
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{
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unsigned timeout = 50; /* 1usec * 50 = 50usec */
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/*
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* Quote from LL TEMAC documentation: The bits in the RDY
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* register are asserted when there is no access in progress.
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* When an access is in progress, a bit corresponding to the
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* type of access is automatically de-asserted. The bit is
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* automatically re-asserted when the access is complete.
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*/
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while (timeout && (!(in_be32(®s->rdy) & mask))) {
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timeout--;
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udelay(1);
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}
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if (!timeout) {
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printf("%s: Timeout on 0x%08x @%p\n", __func__,
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mask, ®s->rdy);
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return 1;
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}
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return 0;
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}
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/*
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* Indirect write to ll_temac.
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*
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* http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf
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* page 23, second paragraph, The use of CTL0 register or CTL1 register
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*/
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int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data)
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{
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out_be32(®s->lsw, (reg_data & MLSW_MASK));
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out_be32(®s->ctl, CTL_WEN | (regn & CTL_ADDR_MASK));
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if (ll_temac_check_status(regs, RSE_CFG_WR))
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return 0;
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return 1;
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}
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/*
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* Indirect read from ll_temac.
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*
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* http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf
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* page 23, second paragraph, The use of CTL0 register or CTL1 register
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*/
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int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data)
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{
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out_be32(®s->ctl, (regn & CTL_ADDR_MASK));
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if (ll_temac_check_status(regs, RSE_CFG_RR))
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return 0;
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*reg_data = in_be32(®s->lsw) & MLSW_MASK;
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return 1;
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}
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/* setting sub-controller and ll_temac to proper setting */
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static int ll_temac_setup_ctrl(struct eth_device *dev)
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{
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struct ll_temac *ll_temac = dev->priv;
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struct temac_reg *regs = (struct temac_reg *)dev->iobase;
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if (ll_temac->ctrlreset && ll_temac->ctrlreset(dev))
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return 0;
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if (ll_temac->ctrlinit && ll_temac->ctrlinit(dev))
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return 0;
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/* Promiscuous mode disable */
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if (!ll_temac_indirect_set(regs, TEMAC_AFM, 0))
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return 0;
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/* Enable Receiver - RX bit */
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if (!ll_temac_indirect_set(regs, TEMAC_RCW1, RCW1_RX))
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return 0;
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/* Enable Transmitter - TX bit */
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if (!ll_temac_indirect_set(regs, TEMAC_TC, TC_TX))
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return 0;
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return 1;
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}
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/*
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* Configure ll_temac based on negotiated speed and duplex
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* reported by PHY handling code
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*/
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static int ll_temac_adjust_link(struct eth_device *dev)
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{
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unsigned int speed, emmc_reg;
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struct temac_reg *regs = (struct temac_reg *)dev->iobase;
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struct ll_temac *ll_temac = dev->priv;
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struct phy_device *phydev = ll_temac->phydev;
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return 0;
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}
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switch (phydev->speed) {
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case 1000:
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speed = EMMC_LSPD_1000;
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break;
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case 100:
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speed = EMMC_LSPD_100;
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break;
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case 10:
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speed = EMMC_LSPD_10;
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break;
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default:
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return 0;
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}
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if (!ll_temac_indirect_get(regs, TEMAC_EMMC, &emmc_reg))
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return 0;
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emmc_reg &= ~EMMC_LSPD_MASK;
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emmc_reg |= speed;
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if (!ll_temac_indirect_set(regs, TEMAC_EMMC, emmc_reg))
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return 0;
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printf("%s: PHY is %s with %dbase%s, %s%s\n",
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dev->name, phydev->drv->name,
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phydev->speed, (phydev->port == PORT_TP) ? "T" : "X",
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(phydev->duplex) ? "FDX" : "HDX",
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(phydev->port == PORT_OTHER) ? ", unkown mode" : "");
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return 1;
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}
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/* setup mac addr */
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static int ll_temac_setup_mac_addr(struct eth_device *dev)
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{
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struct temac_reg *regs = (struct temac_reg *)dev->iobase;
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u32 val;
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/* set up unicast MAC address filter */
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val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) |
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(dev->enetaddr[1] << 8) | (dev->enetaddr[0]));
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val &= UAW0_UADDR_MASK;
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if (!ll_temac_indirect_set(regs, TEMAC_UAW0, val))
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return 1;
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val = ((dev->enetaddr[5] << 8) | dev->enetaddr[4]);
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val &= UAW1_UADDR_MASK;
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if (!ll_temac_indirect_set(regs, TEMAC_UAW1, val))
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return 1;
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return 0;
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}
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/* halt device */
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static void ll_temac_halt(struct eth_device *dev)
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{
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struct ll_temac *ll_temac = dev->priv;
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struct temac_reg *regs = (struct temac_reg *)dev->iobase;
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/* Disable Receiver */
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ll_temac_indirect_set(regs, TEMAC_RCW0, 0);
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/* Disable Transmitter */
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ll_temac_indirect_set(regs, TEMAC_TC, 0);
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if (ll_temac->ctrlhalt)
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ll_temac->ctrlhalt(dev);
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/* Shut down the PHY, as needed */
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phy_shutdown(ll_temac->phydev);
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}
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static int ll_temac_init(struct eth_device *dev, bd_t *bis)
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{
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struct ll_temac *ll_temac = dev->priv;
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int ret;
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printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08lx.\n",
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dev->name, dev->index, dev->iobase);
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if (!ll_temac_setup_ctrl(dev))
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return -1;
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/* Start up the PHY */
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ret = phy_startup(ll_temac->phydev);
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if (ret) {
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printf("%s: Could not initialize PHY %s\n",
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dev->name, ll_temac->phydev->dev->name);
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return ret;
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}
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if (!ll_temac_adjust_link(dev)) {
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ll_temac_halt(dev);
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return -1;
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}
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/* If there's no link, fail */
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return ll_temac->phydev->link ? 0 : -1;
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}
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/*
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* Discover which PHY is attached to the device, and configure it
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* properly. If the PHY is not recognized, then return 0
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* (failure). Otherwise, return 1
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*/
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static int ll_temac_phy_init(struct eth_device *dev)
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{
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struct ll_temac *ll_temac = dev->priv;
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struct phy_device *phydev;
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unsigned int supported = PHY_GBIT_FEATURES;
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/* interface - look at driver/net/tsec.c */
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phydev = phy_connect(ll_temac->bus, ll_temac->phyaddr,
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dev, PHY_INTERFACE_MODE_NONE);
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phydev->supported &= supported;
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phydev->advertising = phydev->supported;
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ll_temac->phydev = phydev;
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phy_config(phydev);
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return 1;
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}
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/*
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* Initialize a single ll_temac devices
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*
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* Returns the result of ll_temac phy interface that were initialized
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*/
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int xilinx_ll_temac_initialize(bd_t *bis, struct ll_temac_info *devinf)
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{
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struct eth_device *dev;
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struct ll_temac *ll_temac;
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dev = calloc(1, sizeof(*dev));
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if (dev == NULL)
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return 0;
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ll_temac = calloc(1, sizeof(struct ll_temac));
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if (ll_temac == NULL) {
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free(dev);
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return 0;
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}
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/* use given name or generate its own unique name */
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if (devinf->devname) {
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strncpy(dev->name, devinf->devname, sizeof(dev->name));
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} else {
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snprintf(dev->name, sizeof(dev->name), "lltemac.%lx", devinf->base_addr);
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devinf->devname = dev->name;
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}
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dev->iobase = devinf->base_addr;
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dev->priv = ll_temac;
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dev->init = ll_temac_init;
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dev->halt = ll_temac_halt;
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dev->write_hwaddr = ll_temac_setup_mac_addr;
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ll_temac->ctrladdr = devinf->ctrl_addr;
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if (devinf->flags & XILINX_LL_TEMAC_M_SDMA_PLB) {
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#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405)
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if (devinf->flags & XILINX_LL_TEMAC_M_SDMA_DCR) {
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ll_temac_collect_xldcr_sdma_reg_addr(dev);
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ll_temac->in32 = ll_temac_xldcr_in32;
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ll_temac->out32 = ll_temac_xldcr_out32;
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} else
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#endif
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{
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ll_temac_collect_xlplb_sdma_reg_addr(dev);
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ll_temac->in32 = ll_temac_xlplb_in32;
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ll_temac->out32 = ll_temac_xlplb_out32;
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}
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ll_temac->ctrlinit = ll_temac_init_sdma;
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ll_temac->ctrlhalt = ll_temac_halt_sdma;
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ll_temac->ctrlreset = ll_temac_reset_sdma;
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dev->recv = ll_temac_recv_sdma;
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dev->send = ll_temac_send_sdma;
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} else {
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ll_temac->in32 = NULL;
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ll_temac->out32 = NULL;
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ll_temac->ctrlinit = NULL;
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ll_temac->ctrlhalt = NULL;
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ll_temac->ctrlreset = ll_temac_reset_fifo;
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dev->recv = ll_temac_recv_fifo;
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dev->send = ll_temac_send_fifo;
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}
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/* Link to specified MDIO bus */
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strncpy(ll_temac->mdio_busname, devinf->mdio_busname, MDIO_NAME_LEN);
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ll_temac->bus = miiphy_get_dev_by_name(ll_temac->mdio_busname);
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/* Looking for a valid PHY address if it is not yet set */
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if (devinf->phyaddr == -1)
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ll_temac->phyaddr = ll_temac_phy_addr(ll_temac->bus);
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else
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ll_temac->phyaddr = devinf->phyaddr;
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eth_register(dev);
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/* Try to initialize PHY here, and return */
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return ll_temac_phy_init(dev);
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}
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/*
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* Initialize a single ll_temac device with its mdio bus behind ll_temac
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*
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* Returns 1 if the ll_temac device and the mdio bus were initialized
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* otherwise returns 0
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*/
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int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
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unsigned long ctrl_addr)
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{
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struct ll_temac_info devinf;
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struct ll_temac_mdio_info mdioinf;
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int ret;
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/* prepare the internal driver informations */
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devinf.flags = flags;
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devinf.base_addr = base_addr;
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devinf.ctrl_addr = ctrl_addr;
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devinf.devname = NULL;
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devinf.phyaddr = -1;
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mdioinf.name = devinf.mdio_busname = NULL;
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mdioinf.regs = (struct temac_reg *)devinf.base_addr;
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ret = xilinx_ll_temac_mdio_initialize(bis, &mdioinf);
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if (ret >= 0) {
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/*
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* If there was no MDIO bus name then take over the
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* new automaticaly generated by the MDIO init code.
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*/
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if (mdioinf.name != devinf.mdio_busname)
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devinf.mdio_busname = mdioinf.name;
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ret = xilinx_ll_temac_initialize(bis, &devinf);
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if (ret > 0)
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return 1;
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}
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return 0;
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}
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