u-boot/arch/xtensa/include/asm/cache.h
Chris Zankel c978b52410 xtensa: add support for the xtensa processor architecture [2/2]
The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Tensilica, inc.

This is the second part of the basic architecture port, adding the
'arch/xtensa' directory and a readme file.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-08-15 18:46:38 -04:00

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C

/*
* Copyright (C) 2009 Tensilica Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _XTENSA_CACHE_H
#define _XTENSA_CACHE_H
#include <asm/arch/core.h>
#define ARCH_DMA_MINALIGN XCHAL_DCACHE_LINESIZE
#ifndef __ASSEMBLY__
void __flush_dcache_all(void);
void __flush_invalidate_dcache_range(unsigned long addr, unsigned long size);
void __invalidate_dcache_all(void);
void __invalidate_dcache_range(unsigned long addr, unsigned long size);
void __invalidate_icache_all(void);
void __invalidate_icache_range(unsigned long addr, unsigned long size);
#endif
#endif /* _XTENSA_CACHE_H */