mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
d4590da436
In the recent dropping of !NET_MULTI code (commit e2a53458a7),
I misread the logic in include/net.h. Some of it was used by NET_MULTI
code as glue between the multi/non-multi worlds for cpm2 boards.
Rather than restore the block of code, push the logic to the board config
headers where it all belongs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
417 lines
14 KiB
C
417 lines
14 KiB
C
/*
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* (C) Copyright 2008
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_8260 1
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#define CONFIG_MPC8260 1
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#define CONFIG_MUAS3001 1
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#define CONFIG_SYS_TEXT_BASE 0xFF000000
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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/* Do boardspecific init */
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#define CONFIG_BOARD_EARLY_INIT_R 1
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/* enable Watchdog */
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#define CONFIG_WATCHDOG 1
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/*
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* Select serial console configuration
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*
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* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*/
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#define CONFIG_CONS_ON_SMC /* Console is on SMC */
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#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
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#undef CONFIG_CONS_NONE /* It's not on external UART */
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#if defined(CONFIG_MUAS_DEV_BOARD)
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#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
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#else
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#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
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#endif
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/*
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* Select ethernet configuration
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*
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* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
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* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
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* SCC, 1-3 for FCC)
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*
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* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
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* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
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* must be unset.
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*/
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#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
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#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
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#undef CONFIG_ETHER_NONE /* No external Ethernet */
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#define CONFIG_ETHER_INDEX 1
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#define CONFIG_ETHER_ON_FCC1
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#define CONFIG_HAS_ETH0
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#define FCC_ENET
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/*
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* - Rx-CLK is CLK11
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* - Tx-CLK is CLK12
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*/
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# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
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# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
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/*
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* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
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*/
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# define CONFIG_SYS_CPMFCR_RAMTYPE (0)
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/* know on local Bus */
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/* define CONFIG_SYS_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */
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/*
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* - Enable Full Duplex in FSMR
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*/
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# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
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# define CONFIG_SYS_PHY_ADDR 1
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/*
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* GPIO pins used for bit-banged MII communications
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*/
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#define MDIO_PORT 0 /* Port A */
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#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
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(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
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#define MDC_DECLARE MDIO_DECLARE
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#define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */
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#define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */
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#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
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#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
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#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
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#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
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else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
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#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
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else iop->pdat &= ~CONFIG_SYS_MDC_PIN
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#define MIIDELAY udelay(1)
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#ifndef CONFIG_8260_CLKIN
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#define CONFIG_8260_CLKIN 66000000 /* in Hz */
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#endif
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#define CONFIG_BAUDRATE 115200
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DTT
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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/*
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* Default environment settings
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"u-boot_addr_r=100000\0" \
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"kernel_addr_r=200000\0" \
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"fdt_addr_r=400000\0" \
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"rootpath=/opt/eldk/ppc_6xx\0" \
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"u-boot=muas3001/u-boot.bin\0" \
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"bootfile=muas3001/uImage\0" \
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"fdt_file=muas3001/muas3001.dtb\0" \
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"ramdisk_file=uRamdisk\0" \
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"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
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"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
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"cp.b ${u-boot_addr_r} ff000000 ${filesize};" \
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"prot on ff000000 ff03ffff\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:" \
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"${netmask}:${hostname}:${netdev}:off panic=1\0" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
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"tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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"net_self=tftp ${kernel_addr_r} ${bootfile}; " \
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"tftp ${fdt_addr_r} ${fdt_file}; " \
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"tftp ${ramdisk_addr} ${ramdisk_file}; " \
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"run ramargs addip; " \
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"bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \
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"ramdisk_addr=ff210000\0" \
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"kernel_addr=ff050000\0" \
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"fdt_addr=ff200000\0" \
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"flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \
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" ${ramdisk_addr} ${fdt_addr}\0" \
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"updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \
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" ${ramdisk_file};" \
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"cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \
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"updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \
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" ${bootfile};" \
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"cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \
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"updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \
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"cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \
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""
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#define CONFIG_BOOTCOMMAND "run net_nfs"
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFF000000
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#define CONFIG_SYS_FLASH_SIZE 32
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
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#define CONFIG_ENV_IS_IN_FLASH
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/*
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* I2C Bus
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*/
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#define CONFIG_HARD_I2C 1 /* To enable I2C support */
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#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CONFIG_SYS_DTT_MAX_TEMP 70
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#define CONFIG_SYS_DTT_LOW_TEMP -30
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#define CONFIG_SYS_DTT_HYSTERESIS 3
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#define CONFIG_SYS_IMMR 0xF0000000
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#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/* Hard reset configuration word */
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#define CONFIG_SYS_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */
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/* No slaves */
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#define CONFIG_SYS_HRCW_SLAVE1 0
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#define CONFIG_SYS_HRCW_SLAVE2 0
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#define CONFIG_SYS_HRCW_SLAVE3 0
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#define CONFIG_SYS_HRCW_SLAVE4 0
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#define CONFIG_SYS_HRCW_SLAVE5 0
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#define CONFIG_SYS_HRCW_SLAVE6 0
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#define CONFIG_SYS_HRCW_SLAVE7 0
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#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#define CONFIG_SYS_HID0_INIT 0
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#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
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#define CONFIG_SYS_HID2 0
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#define CONFIG_SYS_SIUMCR 0x00200000
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#define CONFIG_SYS_BCR 0x004c0000
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#define CONFIG_SYS_SCCR 0x0
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 4-35
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register 5-5
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*-----------------------------------------------------------------------
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* turn on Checkstop Reset Enable
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*/
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#define CONFIG_SYS_RMR 0
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*/
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#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RCCR 0
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/*
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* Init Memory Controller:
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*
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* Bank Bus Machine PortSz Device
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* ---- --- ------- ------ ------
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* 0 60x GPCM 32 bit FLASH
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* 1 60x SDRAM 64 bit SDRAM
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* 4 60x GPCM 16 bit I/O Ctrl
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*
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*/
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/* Bank 0 - FLASH
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*/
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#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
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BRx_PS_32 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CONFIG_SYS_OR0_PRELIM (0xff000020)
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/* Bank 1 - 60x bus SDRAM
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*/
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#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
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#define CONFIG_SYS_MPTPR 0x2800
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/*-----------------------------------------------------------------------------
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* Address for Mode Register Set (MRS) command
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*-----------------------------------------------------------------------------
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*/
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#define CONFIG_SYS_MRS_OFFS 0x00000110
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#define CONFIG_SYS_PSRT 0x13
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#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_SDRAM_P |\
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BRx_V)
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_LITTLE
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/* SDRAM initialization values
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*/
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#define CONFIG_SYS_OR1_LITTLE ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI1_A7 |\
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ORxS_NUMR_12)
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#define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3
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#define CONFIG_SYS_OR1_BIG ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI1_A4 |\
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ORxS_NUMR_12)
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#define CONFIG_SYS_PSDMR_BIG 0x014f36a3
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/* IO on CS4 initialization values
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*/
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#define CONFIG_SYS_IO_BASE 0xc0000000
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#define CONFIG_SYS_IO_SIZE 1
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#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
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BRx_PS_16 | BRx_MS_GPCM_L | BRx_V)
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#define CONFIG_SYS_OR4_PRELIM (0xfff80020)
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#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#if defined(CONFIG_MUAS_DEV_BOARD)
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#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
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#else
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#define OF_STDOUT_PATH "/soc/cpm/serial@11a80"
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#endif
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#endif /* __CONFIG_H */
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