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https://github.com/AsahiLinux/u-boot
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e04f9d0c2f
This patch updates clk_adjust to actual value for boards with T-series and LS-series SoCs to match the setting of clk_adjust in latest ddr driver. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
47 lines
1.3 KiB
C
47 lines
1.3 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DDR_H__
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#define __DDR_H__
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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};
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/*
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* These tables contain all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
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*/
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{2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
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{2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
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{2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
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{2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
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{2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
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{1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
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{1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
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{1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
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{1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
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{1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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};
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#endif
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