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https://github.com/AsahiLinux/u-boot
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96c5f0816a
Additionally the SDRAM address decoding register address is not hard coded in the C code any more. A define is introduced for this base address. This makes is possible to use those gpio functions from other MVEBU SoC's as well. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
132 lines
3 KiB
C
132 lines
3 KiB
C
/*
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* Copyright (C) 2011
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* Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
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*
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* Based on Kirkwood support:
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/arch/gpio.h>
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#include "dns325.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/* Gpio configuration */
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mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
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DNS325_OE_LOW, DNS325_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO,
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_SD_CLK,
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MPP13_SD_CMD,
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MPP14_SD_D0,
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MPP15_SD_D1,
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MPP16_SD_D2,
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MPP17_SD_D3,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_SATA1_ACTn, /* sata1(left) status led */
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MPP21_SATA0_ACTn, /* sata0(right) status led */
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MPP22_GPIO,
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MPP23_GPIO,
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MPP24_GPIO, /* power off out */
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MPP25_GPIO,
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MPP26_GPIO, /* power led */
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MPP27_GPIO, /* sata0(right) error led */
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MPP28_GPIO, /* sata1(left) error led */
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MPP29_GPIO, /* usb error led */
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MPP30_GPIO,
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MPP31_GPIO,
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MPP32_GPIO,
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MPP33_GPIO,
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MPP34_GPIO, /* power key */
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MPP35_GPIO,
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MPP36_GPIO,
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MPP37_GPIO,
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MPP38_GPIO,
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MPP39_GPIO, /* enable sata 0 */
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MPP40_GPIO, /* enable sata 1 */
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MPP41_GPIO, /* hdd0 present */
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MPP42_GPIO, /* hdd1 present */
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MPP43_GPIO, /* usb status led */
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MPP44_GPIO, /* fan status */
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MPP45_GPIO, /* fan high speed */
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MPP46_GPIO, /* fan low speed */
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MPP47_GPIO, /* usb umount */
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MPP48_GPIO, /* factory reset */
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MPP49_GPIO, /* thermal sensor */
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
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kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
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return 0;
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}
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int board_init(void)
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{
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/* Boot parameters address */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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/* Configure and initialize PHY */
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void reset_phy(void)
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{
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u16 reg;
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u16 devadr;
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char *name = "egiga0";
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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printf("Err..(%s) could not read PHY dev address\n", __func__);
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, devadr);
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debug("88E1116 Initialized on %s\n", name);
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}
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#endif /* CONFIG_RESET_PHY_R */
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