mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 14:23:00 +00:00
8f5d468721
add support for printing various clock frequency info found in SOC such as ARM core frequency, DSP core frequency and DDR frequency as part of bdinfo command. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Cc: Tom Rini <trini@ti.com>
156 lines
5.9 KiB
C
156 lines
5.9 KiB
C
/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
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* Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* Board */
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#define SFFSDR
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#define CONFIG_SYS_NAND_LARGEPAGE
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#define CONFIG_SYS_USE_NAND
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#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
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/* SoC Configuration */
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#define CONFIG_ARM926EJS /* arm926ejs CPU core */
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#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
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#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SOC_DM644X
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/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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/* Memory Info */
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#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
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#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
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#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define CONFIG_STACKSIZE (256*1024) /* regular stack */
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#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
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#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
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/* Serial Driver info */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
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#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
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#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
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#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
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#define CONFIG_BAUDRATE 115200 /* Default baud rate */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* I2C Configuration */
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#define CONFIG_HARD_I2C
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#define CONFIG_DRIVER_DAVINCI_I2C
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#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
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#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
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/* Network & Ethernet Configuration */
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_MII
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#define CONFIG_BOOTP_DEFAULT
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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/* Flash & Environment */
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#undef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_NAND_DAVINCI
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#define CONFIG_SYS_NAND_CS 2
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#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
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#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
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#define CONFIG_SYS_NAND_BASE 0x02000000
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#define CONFIG_SYS_NAND_HW_ECC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
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/* I2C switch definitions for PCA9543 chip */
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#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
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#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
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#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
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/* U-Boot general configuration */
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#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel
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* load address. */
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#define CONFIG_VERSION_VARIABLE
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#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far,
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* may be later */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CRC32_VERIFY
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#define CONFIG_MX_CYCLIC
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/* Linux Information */
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#define LINUX_BOOT_PARAM_ADDR 0x80000100
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_BOOTARGS \
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"mem=56M " \
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"console=ttyS0,115200n8 " \
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"root=/dev/nfs rw noinitrd ip=dhcp " \
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"nfsroot=${serverip}:/nfsroot/sffsdr " \
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"eth0=${ethaddr}"
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#define CONFIG_BOOTCOMMAND \
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"nand read 87A00000 100000 300000;" \
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"bootelf 87A00000"
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/* U-Boot commands */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SAVES
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_SETGETDCR
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_IMLS
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#ifdef CONFIG_CMD_BDI
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#define CONFIG_CLOCKS
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#endif
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#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#endif /* __CONFIG_H */
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