mirror of
https://github.com/AsahiLinux/u-boot
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0d98f6de62
This documentation has been taken from Linux commit 3d7db0f11c7a ("spi: dw:
Refactor mid_spi_dma_setup() to separate DMA and IRQ config"), immediately
before the file was deleted and replaced with a yaml version. Additional
compatible strings from newer versions have been added, as well as a few
U-Boot-specific ones.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
56 lines
2 KiB
Text
56 lines
2 KiB
Text
Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
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and Synopsys DesignWare High Performance Synchronous Serial Interface
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Required properties:
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- compatible : One of
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"altr,socfpga-spi",
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"altr,socfpga-arria10-spi",
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"canaan,kendryte-k210-spi",
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"canaan,kendryte-k210-ssi",
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"intel,stratix10-spi",
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"intel,agilex-spi",
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"mscc,ocelot-spi",
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or "mscc,jaguar2-spi";
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and one of
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"snps,dw-apb-ssi-3.20a",
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"snps,dw-apb-ssi-3.22a",
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"snps,dw-apb-ssi-3.23",
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"snps,dw-apb-ssi-4.00a",
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"snps,dw-apb-ssi-4.01",
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or "snps,dwc-ssi-1.01a".
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"snps,dw-apb-ssi" may also be used, but is deprecated in favor of specific
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version strings.
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- reg : The register base for the controller. For "mscc,<soc>-spi", a second
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register set is required (named ICPU_CFG:SPI_MST)
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- #address-cells : <1>, as required by generic SPI binding.
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- #size-cells : <0>, also as required by generic SPI binding.
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- clocks : phandles for the clocks, see the description of clock-names below.
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The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
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is optional. If a single clock is specified but no clock-name, it is the
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"ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
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Optional properties:
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- clock-names : Contains the names of the clocks:
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"ssi_clk", for the core clock used to generate the external SPI clock.
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"pclk", the interface clock, required for register access.
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- cs-gpios : Specifies the gpio pins to be used for chipselects.
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- num-cs : The number of chipselects. If omitted, this will default to 4.
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- reg-io-width : The I/O register width (in bytes) implemented by this
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device. Supported values are 2 or 4 (the default).
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Child nodes as per the generic SPI binding.
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Example:
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spi@fff00000 {
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compatible = "altr,socfpga-arria10-spi",
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"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 154 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&spi_m_clk>;
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num-cs = <2>;
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cs-gpios = <&gpio0 13 0>,
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<&gpio0 14 0>;
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};
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