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https://github.com/AsahiLinux/u-boot
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d5db46cf93
The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
138 lines
3.3 KiB
C
138 lines
3.3 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Clock drivers for Qualcomm APQ8096
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*
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* (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
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*
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* Based on Little Kernel driver, simplified
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include "clock-qcom.h"
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/* Clocks: (from CLK_CTL_BASE) */
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#define GPLL0_STATUS (0x0000)
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#define APCS_GPLL_ENA_VOTE (0x52000)
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#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004)
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#define SDCC2_BCR (0x14000) /* block reset */
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#define SDCC2_APPS_CBCR (0x14004) /* branch control */
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#define SDCC2_AHB_CBCR (0x14008)
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#define SDCC2_CMD_RCGR (0x14010)
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#define SDCC2_CFG_RCGR (0x14014)
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#define SDCC2_M (0x14018)
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#define SDCC2_N (0x1401C)
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#define SDCC2_D (0x14020)
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#define BLSP2_AHB_CBCR (0x25004)
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#define BLSP2_UART2_APPS_CBCR (0x29004)
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#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C)
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#define BLSP2_UART2_APPS_CFG_RCGR (0x29010)
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#define BLSP2_UART2_APPS_M (0x29014)
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#define BLSP2_UART2_APPS_N (0x29018)
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#define BLSP2_UART2_APPS_D (0x2901C)
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/* GPLL0 clock control registers */
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#define GPLL0_STATUS_ACTIVE BIT(30)
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#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
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static const struct bcr_regs sdc_regs = {
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.cfg_rcgr = SDCC2_CFG_RCGR,
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.cmd_rcgr = SDCC2_CMD_RCGR,
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.M = SDCC2_M,
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.N = SDCC2_N,
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.D = SDCC2_D,
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};
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static const struct pll_vote_clk gpll0_vote_clk = {
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.status = GPLL0_STATUS,
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.status_bit = GPLL0_STATUS_ACTIVE,
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.ena_vote = APCS_GPLL_ENA_VOTE,
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.vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
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};
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static struct vote_clk gcc_blsp2_ahb_clk = {
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.cbcr_reg = BLSP2_AHB_CBCR,
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.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
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.vote_bit = BIT(15),
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};
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static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
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{
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int div = 5;
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clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
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clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
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CFG_CLK_SRC_GPLL0, 8);
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clk_enable_gpll0(priv->base, &gpll0_vote_clk);
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clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
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return rate;
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}
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static const struct bcr_regs uart2_regs = {
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.cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR,
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.cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR,
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.M = BLSP2_UART2_APPS_M,
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.N = BLSP2_UART2_APPS_N,
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.D = BLSP2_UART2_APPS_D,
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};
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static int clk_init_uart(struct msm_clk_priv *priv)
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{
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/* Enable AHB clock */
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clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk);
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/* 7372800 uart block clock @ GPLL0 */
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clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625,
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CFG_CLK_SRC_GPLL0, 16);
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/* Vote for gpll0 clock */
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clk_enable_gpll0(priv->base, &gpll0_vote_clk);
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/* Enable core clk */
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clk_enable_cbc(priv->base + BLSP2_UART2_APPS_CBCR);
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return 0;
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}
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static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case 0: /* SDC1 */
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return clk_init_sdc(priv, rate);
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break;
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case 4: /*UART2*/
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return clk_init_uart(priv);
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default:
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return 0;
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}
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}
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static struct msm_clk_data apq8096_clk_data = {
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.set_rate = apq8096_clk_set_rate,
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};
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static const struct udevice_id gcc_apq8096_of_match[] = {
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{
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.compatible = "qcom,gcc-apq8096",
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.data = (ulong)&apq8096_clk_data,
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},
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{ }
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};
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U_BOOT_DRIVER(gcc_apq8096) = {
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.name = "gcc_apq8096",
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.id = UCLASS_NOP,
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.of_match = gcc_apq8096_of_match,
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.bind = qcom_cc_bind,
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.flags = DM_FLAG_PRE_RELOC,
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};
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