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https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
175 lines
4 KiB
C
175 lines
4 KiB
C
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_AVR32_ARCH_CLK_H__
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#define __ASM_AVR32_ARCH_CLK_H__
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#include <asm/arch/chip-features.h>
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#include <asm/arch/portmux.h>
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#ifdef CONFIG_PLL
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#define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \
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* CONFIG_SYS_PLL0_MUL)
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#define MAIN_CLK_RATE PLL0_RATE
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#else
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#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
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#endif
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static inline unsigned long get_cpu_clk_rate(void)
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{
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return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU;
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}
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static inline unsigned long get_hsb_clk_rate(void)
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{
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return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB;
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}
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static inline unsigned long get_pba_clk_rate(void)
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{
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return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA;
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}
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static inline unsigned long get_pbb_clk_rate(void)
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{
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return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB;
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}
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/* Accessors for specific devices. More will be added as needed. */
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static inline unsigned long get_sdram_clk_rate(void)
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{
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return get_hsb_clk_rate();
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}
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#ifdef AT32AP700x_CHIP_HAS_USART
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static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
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{
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return get_pba_clk_rate();
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}
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#endif
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#ifdef AT32AP700x_CHIP_HAS_MACB
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static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
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{
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return get_pbb_clk_rate();
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}
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static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
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{
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return get_hsb_clk_rate();
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}
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#endif
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#ifdef AT32AP700x_CHIP_HAS_MMCI
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static inline unsigned long get_mci_clk_rate(void)
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{
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return get_pbb_clk_rate();
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}
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#endif
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#ifdef AT32AP700x_CHIP_HAS_SPI
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static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
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{
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return get_pba_clk_rate();
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}
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#endif
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#ifdef AT32AP700x_CHIP_HAS_LCDC
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static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
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{
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return get_hsb_clk_rate();
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}
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#endif
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extern void clk_init(void);
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/* Board code may need the SDRAM base clock as a compile-time constant */
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#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
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/* Generic clock control */
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enum gclk_parent {
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GCLK_PARENT_OSC0 = 0,
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GCLK_PARENT_OSC1 = 1,
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GCLK_PARENT_PLL0 = 2,
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GCLK_PARENT_PLL1 = 3,
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};
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/* Some generic clocks have specific roles */
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#define GCLK_DAC_SAMPLE_CLK 6
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#define GCLK_LCDC_PIXCLK 7
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extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
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unsigned long rate, unsigned long parent_rate);
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/**
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* gclk_set_rate - configure and enable a generic clock
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* @id: Which GCLK[id] to enable
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* @parent: Parent clock feeding the GCLK
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* @rate: Target rate of the GCLK in Hz
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*
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* Returns the actual GCLK rate in Hz, after rounding to the nearest
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* supported rate.
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*
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* All three parameters are usually constant, hence the inline.
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*/
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static inline unsigned long gclk_set_rate(unsigned int id,
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enum gclk_parent parent, unsigned long rate)
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{
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unsigned long parent_rate;
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if (id > 7)
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return 0;
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switch (parent) {
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case GCLK_PARENT_OSC0:
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parent_rate = CONFIG_SYS_OSC0_HZ;
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break;
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#ifdef CONFIG_SYS_OSC1_HZ
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case GCLK_PARENT_OSC1:
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parent_rate = CONFIG_SYS_OSC1_HZ;
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break;
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#endif
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#ifdef PLL0_RATE
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case GCLK_PARENT_PLL0:
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parent_rate = PLL0_RATE;
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break;
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#endif
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#ifdef PLL1_RATE
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case GCLK_PARENT_PLL1:
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parent_rate = PLL1_RATE;
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break;
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#endif
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default:
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parent_rate = 0;
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break;
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}
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return __gclk_set_rate(id, parent, rate, parent_rate);
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}
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/**
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* gclk_enable_output - enable output on a GCLK pin
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* @id: Which GCLK[id] pin to enable
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* @drive_strength: Drive strength of external GCLK pin, if applicable
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*/
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static inline void gclk_enable_output(unsigned int id,
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unsigned long drive_strength)
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{
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switch (id) {
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case 0:
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portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
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PORTMUX_FUNC_A, drive_strength);
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break;
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case 1:
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portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
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PORTMUX_FUNC_A, drive_strength);
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break;
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case 2:
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portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
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PORTMUX_FUNC_A, drive_strength);
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break;
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case 3:
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portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
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PORTMUX_FUNC_A, drive_strength);
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break;
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case 4:
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portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
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PORTMUX_FUNC_A, drive_strength);
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break;
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}
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}
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#endif /* __ASM_AVR32_ARCH_CLK_H__ */
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