mirror of
https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
231 lines
6.8 KiB
C
231 lines
6.8 KiB
C
/*
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* (C) Copyright 2000-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <asm/io.h>
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#include <watchdog.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers.
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*/
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void cpu_init_f (void)
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{
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volatile struct mpc5xxx_mmap_ctl *mm =
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(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
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volatile struct mpc5xxx_lpb *lpb =
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(struct mpc5xxx_lpb *) MPC5XXX_LPB;
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volatile struct mpc5xxx_gpio *gpio =
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(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
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volatile struct mpc5xxx_xlb *xlb =
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(struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
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#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
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volatile struct mpc5xxx_cdm *cdm =
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(struct mpc5xxx_cdm *) MPC5XXX_CDM;
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#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
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#if defined(CONFIG_WATCHDOG)
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volatile struct mpc5xxx_gpt *gpt0 =
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(struct mpc5xxx_gpt *) MPC5XXX_GPT;
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#endif /* CONFIG_WATCHDOG */
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unsigned long addecr = (1 << 25); /* Boot_CS */
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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/*
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* Memory Controller: configure chip selects and enable them
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*/
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#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
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out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
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out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
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CONFIG_SYS_BOOTCS_SIZE));
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#endif
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#if defined(CONFIG_SYS_BOOTCS_CFG)
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out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
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#endif
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#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
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out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
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out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
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CONFIG_SYS_CS0_SIZE));
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/* CS0 and BOOT_CS cannot be enabled at once. */
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/* addecr |= (1 << 16); */
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#endif
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#if defined(CONFIG_SYS_CS0_CFG)
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out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
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#endif
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#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
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out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
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out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
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CONFIG_SYS_CS1_SIZE));
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addecr |= (1 << 17);
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#endif
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#if defined(CONFIG_SYS_CS1_CFG)
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out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
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#endif
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#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
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out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
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out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
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CONFIG_SYS_CS2_SIZE));
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addecr |= (1 << 18);
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#endif
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#if defined(CONFIG_SYS_CS2_CFG)
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out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
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#endif
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#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
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out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
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out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
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CONFIG_SYS_CS3_SIZE));
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addecr |= (1 << 19);
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#endif
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#if defined(CONFIG_SYS_CS3_CFG)
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out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
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#endif
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#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
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out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
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out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
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CONFIG_SYS_CS4_SIZE));
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addecr |= (1 << 20);
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#endif
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#if defined(CONFIG_SYS_CS4_CFG)
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out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
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#endif
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#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
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out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
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out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
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CONFIG_SYS_CS5_SIZE));
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addecr |= (1 << 21);
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#endif
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#if defined(CONFIG_SYS_CS5_CFG)
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out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
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#endif
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addecr |= 1;
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#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
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out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
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out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
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CONFIG_SYS_CS6_SIZE));
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addecr |= (1 << 26);
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#endif
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#if defined(CONFIG_SYS_CS6_CFG)
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out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
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#endif
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#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
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out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
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out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
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CONFIG_SYS_CS7_SIZE));
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addecr |= (1 << 27);
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#endif
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#if defined(CONFIG_SYS_CS7_CFG)
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out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
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#endif
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#if defined(CONFIG_SYS_CS_BURST)
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out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
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#endif
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#if defined(CONFIG_SYS_CS_DEADCYCLE)
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out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
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#endif
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/* Enable chip selects */
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out_be32(&mm->ipbi_ws_ctrl, addecr);
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out_be32(&lpb->cs_ctrl, (1 << 24));
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/* Setup pin multiplexing */
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#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
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out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
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#endif
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/* Setup gpios */
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#if defined(CONFIG_SYS_GPIO_DATADIR)
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out_be32(&gpio->simple_ddr, CONFIG_SYS_GPIO_DATADIR);
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#endif
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#if defined(CONFIG_SYS_GPIO_OPENDRAIN)
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out_be32(&gpio->simple_ode, CONFIG_SYS_GPIO_OPENDRAIN);
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#endif
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#if defined(CONFIG_SYS_GPIO_DATAVALUE)
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out_be32(&gpio->simple_dvo, CONFIG_SYS_GPIO_DATAVALUE);
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#endif
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#if defined(CONFIG_SYS_GPIO_ENABLE)
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out_be32(&gpio->simple_gpioe, CONFIG_SYS_GPIO_ENABLE);
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#endif
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/* enable timebase */
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setbits_be32(&xlb->config, (1 << 13));
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/* Enable snooping for RAM */
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setbits_be32(&xlb->config, (1 << 15));
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out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
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#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
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/* Motorola reports IPB should better run at 133 MHz. */
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setbits_be32(&mm->ipbi_ws_ctrl, 1);
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/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
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addecr = in_be32(&cdm->cfg);
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addecr &= ~0x103;
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# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
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/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
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addecr |= 0x01;
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# else
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/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
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addecr |= 0x02;
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# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
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out_be32(&cdm->cfg, addecr);
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#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
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/* Configure the XLB Arbiter */
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out_be32(&xlb->master_pri_enable, 0xff);
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out_be32(&xlb->master_priority, 0x11111111);
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#if defined(CONFIG_SYS_XLB_PIPELINING)
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/* Enable piplining */
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clrbits_be32(&xlb->config, (1 << 31));
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#endif
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#if defined(CONFIG_WATCHDOG)
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/* Charge the watchdog timer - prescaler = 64k, count = 64k*/
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out_be32(&gpt0->cir, 0x0000ffff);
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out_be32(&gpt0->emsr, 0x9004); /* wden|ce|timer_ms */
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reset_5xxx_watchdog();
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#endif /* CONFIG_WATCHDOG */
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}
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/*
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* initialize higher level parts of CPU like time base and timers
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*/
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int cpu_init_r (void)
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{
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volatile struct mpc5xxx_intr *intr =
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(struct mpc5xxx_intr *) MPC5XXX_ICTL;
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/* mask all interrupts */
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out_be32(&intr->per_mask, 0xffffff00);
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setbits_be32(&intr->main_mask, 0x0001ffff);
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clrbits_be32(&intr->ctrl, 0x00000f00);
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/* route critical ints to normal ints */
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setbits_be32(&intr->ctrl, 0x00000001);
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
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/* load FEC microcode */
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loadtask(0, 2);
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#endif
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return (0);
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}
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