mirror of
https://github.com/AsahiLinux/u-boot
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7ffe3cd62e
Since CONFIG_OF_BOARD_SETUP depends on CONFIG_OF_LIBFDT:
config OF_BOARD_SETUP
bool "Set up board-specific details in device tree before boot"
depends on OF_LIBFDT
...
remove superfluous tests of CONFIG_OF_LIBFDT when testing for
CONFIG_OF_BOARD_SETUP.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
[trini: Typo fix: s/ifdefi/ifdef/]
Signed-off-by: Tom Rini <trini@konsulko.com>
168 lines
3.8 KiB
C
168 lines
3.8 KiB
C
/*
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* (C) Copyright 2000-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* CPU specific code for the MPC5xxx CPUs
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <net.h>
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#include <mpc5xxx.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#include <fdt_support.h>
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#endif
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#if defined(CONFIG_OF_IDE_FIXUP)
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#include <ide.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int checkcpu (void)
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{
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ulong clock = gd->cpu_clk;
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char buf[32];
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uint svr, pvr;
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puts ("CPU: ");
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svr = get_svr();
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pvr = get_pvr();
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switch (pvr) {
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case PVR_5200:
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printf("MPC5200");
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break;
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case PVR_5200B:
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printf("MPC5200B");
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break;
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default:
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printf("Unknown MPC5xxx");
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break;
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}
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printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
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PVR_MAJ(pvr), PVR_MIN(pvr));
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printf (" at %s MHz\n", strmhz (buf, clock));
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int
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do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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ulong msr;
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/* Interrupts and MMU off */
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__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
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msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
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__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
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/* Charge the watchdog timer */
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*(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f;
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*(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */
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while(1);
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return 1;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Get timebase clock frequency (like cpu_clk in Hz)
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*
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*/
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unsigned long get_tbclk (void)
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{
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ulong tbclk;
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tbclk = (gd->bus_clk + 3L) / 4L;
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return (tbclk);
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}
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_OF_BOARD_SETUP
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4;
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char * cpu_path = "/cpus/" OF_CPU;
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#ifdef CONFIG_MPC5xxx_FEC
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uchar enetaddr[6];
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char * eth_path = "/" OF_SOC "/ethernet@3000";
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#endif
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do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
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do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
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do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
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do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1);
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do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency",
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bd->bi_busfreq*div, 1);
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#ifdef CONFIG_MPC5xxx_FEC
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eth_getenv_enetaddr("ethaddr", enetaddr);
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do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0);
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do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0);
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#endif
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#ifdef CONFIG_OF_IDE_FIXUP
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if (!ide_device_present(0)) {
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/* NO CF card detected -> delete ata node in DTS */
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int nodeoffset = 0;
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char nodename[] = "/soc5200@f0000000/ata@3a00";
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nodeoffset = fdt_path_offset(blob, nodename);
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if (nodeoffset >= 0) {
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fdt_del_node(blob, nodeoffset);
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} else {
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printf("%s: cannot find %s node err:%s\n",
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__func__, nodename, fdt_strerror(nodeoffset));
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}
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}
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#endif /* CONFIG_OF_IDE_FIXUP */
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fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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#ifdef CONFIG_MPC5xxx_FEC
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/* Default initializations for FEC controllers. To override,
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* create a board-specific function called:
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* int board_eth_init(bd_t *bis)
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*/
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int cpu_eth_init(bd_t *bis)
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{
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return mpc5xxx_fec_initialize(bis);
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}
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#endif
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#if defined(CONFIG_WATCHDOG)
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void watchdog_reset(void)
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{
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int re_enable = disable_interrupts();
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reset_5xxx_watchdog();
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if (re_enable) enable_interrupts();
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}
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void reset_5xxx_watchdog(void)
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{
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volatile struct mpc5xxx_gpt *gpt0 =
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(struct mpc5xxx_gpt *) MPC5XXX_GPT;
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/* Trigger TIMER_0 by writing A5 to OCPW */
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clrsetbits_be32(&gpt0->emsr, 0xff000000, 0xa5000000);
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}
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#endif /* CONFIG_WATCHDOG */
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