mirror of
https://github.com/AsahiLinux/u-boot
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0159995841
According to the README: "- CONFIG_SYS_SPD_BUS_NUM If SPD EEPROM is on an I2C bus other than the first one, specify here. Note that the value must resolve to something your driver can deal with." There is no SPD EEPROM on the imx boards, so ged rid of this option. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
143 lines
3.6 KiB
C
143 lines
3.6 KiB
C
/*
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* (C) Copyright 2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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/* High Level Configuration Options */
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#define CONFIG_MX25
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#define CONFIG_SYS_TEXT_BASE 0x81200000
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#define CONFIG_MXC_GPIO
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#define CONFIG_SYS_TIMER_RATE 32768
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#define CONFIG_SYS_TIMER_COUNTER \
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(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_MACH_TYPE MACH_TYPE_MX25_3DS
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x80000000
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#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR IMX_RAM_BASE
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#define CONFIG_SYS_INIT_RAM_SIZE IMX_RAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* Memory Test */
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE/2)
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
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/* Serial Info */
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
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#define CONFIG_BAUDRATE 115200 /* Default baud rate */
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/* No NOR flash present */
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#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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/* U-Boot general configuration */
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print buffer sz */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_LONGHELP
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/* U-Boot commands */
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#include <config_cmd_default.h>
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#define CONFIG_OF_LIBFDT
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#define CONFIG_CMD_BOOTZ
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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/* Ethernet */
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_MXC_PHYADDR 0x1f
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#define CONFIG_MII
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#define CONFIG_CMD_NET
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#define CONFIG_ENV_OVERWRITE
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/* ESDHC driver */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_ESDHC_NUM 1
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/* PMIC Configs */
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_FSL
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#define CONFIG_PMIC_FSL_MC34704
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#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54
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#define CONFIG_DOS_PARTITION
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/* I2C Configs */
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#define CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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/* RTC */
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#define CONFIG_RTC_IMXDI
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#define CONFIG_CMD_DATE
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/* Ethernet Configs */
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_BOOTDELAY 1
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#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"uimage=uImage\0" \
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"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"bootcmd=run netargs; dhcp ${uimage}; bootm\0" \
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#endif /* __CONFIG_H */
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