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https://github.com/AsahiLinux/u-boot
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de1d0a6995
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276 lines
6.3 KiB
C
276 lines
6.3 KiB
C
/*
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* Copyright Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Change log:
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* 20050101: Eran Liberty (liberty@freescale.com)
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* Initial file creating (porting from 85XX & 8260)
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#include <i2c.h>
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#include <spd.h>
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#include <miiphy.h>
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#if defined(CONFIG_PCI)
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#include <pci.h>
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#endif
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#if defined(CONFIG_SPD_EEPROM)
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#include <spd_sdram.h>
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#endif
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int fixed_sdram(void);
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void sdram_init(void);
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int board_early_init_f (void)
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{
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volatile u8* bcsr = (volatile u8*)CFG_BCSR;
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/* Enable flash write */
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bcsr[1] &= ~0x01;
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return 0;
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}
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#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
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long int initdram (int board_type)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram(NULL);
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#else
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msize = fixed_sdram();
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#endif
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/*
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* Initialize SDRAM if it is on local bus.
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*/
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sdram_init();
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puts(" DDR RAM: ");
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/* return total bus SDRAM size(bytes) -- DDR */
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return (msize * 1024 * 1024);
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CFG_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1);
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ddr_size = ddr_size>>1, ddr_size_log2++) {
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if (ddr_size & 1) {
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return -1;
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}
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}
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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#if (CFG_DDR_SIZE != 256)
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#warning Currenly any ddr size other than 256 is not supported
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#endif
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im->ddr.csbnds[0].csbnds = 0x00100017;
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im->ddr.csbnds[1].csbnds = 0x0018001f;
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im->ddr.csbnds[2].csbnds = 0x00000007;
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im->ddr.csbnds[3].csbnds = 0x0008000f;
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im->ddr.cs_config[0] = CFG_DDR_CONFIG;
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im->ddr.cs_config[1] = CFG_DDR_CONFIG;
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im->ddr.cs_config[2] = CFG_DDR_CONFIG;
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im->ddr.cs_config[3] = CFG_DDR_CONFIG;
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im->ddr.timing_cfg_1 =
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3 << TIMING_CFG1_PRETOACT_SHIFT |
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7 << TIMING_CFG1_ACTTOPRE_SHIFT |
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3 << TIMING_CFG1_ACTTORW_SHIFT |
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4 << TIMING_CFG1_CASLAT_SHIFT |
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3 << TIMING_CFG1_REFREC_SHIFT |
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3 << TIMING_CFG1_WRREC_SHIFT |
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2 << TIMING_CFG1_ACTTOACT_SHIFT |
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1 << TIMING_CFG1_WRTORD_SHIFT;
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im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
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im->ddr.sdram_cfg =
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SDRAM_CFG_SREN
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#if defined(CONFIG_DDR_2T_TIMING)
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| SDRAM_CFG_2T_EN
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#endif
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| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
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im->ddr.sdram_mode =
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0x2000 << SDRAM_MODE_ESD_SHIFT |
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0x0162 << SDRAM_MODE_SD_SHIFT;
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im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT |
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0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
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udelay(200);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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return msize;
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}
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#endif/*!CFG_SPD_EEPROM*/
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int checkboard (void)
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{
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puts("Board: Freescale MPC8349ADS\n");
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return 0;
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}
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI Devices, report devices found
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_mpc83xxads_config_table[] = {
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{PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
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pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
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} },
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{}
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}
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#endif
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volatile static struct pci_controller hose[] = {
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{
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc83xxads_config_table,
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#endif
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},
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{
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc83xxads_config_table,
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#endif
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}
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};
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#endif /* CONFIG_PCI */
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void
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pci_init_board(void)
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{
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#ifdef CONFIG_PCI
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extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
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pci_mpc83xx_init(hose);
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#endif /* CONFIG_PCI */
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}
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/*
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* if MPC8349ADS is soldered with SDRAM
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*/
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#if defined(CFG_BR2_PRELIM) \
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&& defined(CFG_OR2_PRELIM) \
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&& defined(CFG_LBLAWBAR2_PRELIM) \
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&& defined(CFG_LBLAWAR2_PRELIM)
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void
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sdram_init(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
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volatile lbus8349_t *lbc= &immap->lbus;
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uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
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puts("\n SDRAM on Local Bus: ");
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print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
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/*
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* Setup SDRAM Base and Option Registers, already done in cpu_init.c
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*/
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/*setup mtrpt, lsrt and lbcr for LB bus*/
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lbc->lbcr = CFG_LBC_LBCR;
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lbc->mrtpr = CFG_LBC_MRTPR;
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lbc->lsrt = CFG_LBC_LSRT;
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asm("sync");
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/*
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* Configure the SDRAM controller Machine Mode Register.
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*/
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lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/
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lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/
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asm("sync");
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/*1 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*2 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*3 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*4 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*5 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*6 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*7 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*8 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/* 0x58636733;mode register write operation */
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lbc->lsdmr = CFG_LBC_LSDMR_4;
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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}
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#else
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void
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sdram_init(void)
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{
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put("SDRAM on Local Bus is NOT available!\n");
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}
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#endif
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